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Assignment On State Machine Positive Edge Triggered
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Added on 2019-09-25
Assignment On State Machine Positive Edge Triggered
Added on 2019-09-25
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1 Introduction 1.1 Specification The system you design cycles through and displays the first five digits of a number—any number you want. For example, you could use five digits from your own or your lab partner’s student number or phone number. Your submitted code may be stored on computers outside of Canada. If you are concerned about privacy, use a random five digit number. The goal is that each cycle, the LCD on your DE1-SoC willdisplay one digit of this five digit number. The clock input to your state machine should come from pushbutton switch KEY0 onyour DE1-SoC. Every time you press switch KEY0, another number should appear. If the first five digits of your number is “60412”, the LED should display a “6” one the first cycle, then “0” in the second cycle, then a “4” in the third cycle, etc. On the sixth cycle, it should cycle back to “6” and start again. The seven segments of the seven segment display are each controlled by each bit of HEX0[6:0]. A segment turns on if the corresponding bit is 0 and off when that bit is 1 (this might be opposite to what you would expect). The mapping from bits of HEX0 to segments can be seen on the right side of Figure 1. To add a bit of a challenge (and make the lab more fun), the user (i.e., your TA) should be able to change the “direction” of cycling through the digits using slider switch SW0 on your DE1-SoC. If this switch is “up” (corresponding to logic value “1”), the system operates as described above. If this switch is “down” (corresponding to a logic value of “0”), the system should cycle “backwards” (but still starts with the first character). So, in the above example the order would be “621406”. To make things even more interesting (and fun), the user should be able to change the slider switch during any cycle. So, for example, you might go “forwards” for 4 cycles, “backwards” for 2 cycles, and “forwards” for 4 cycles, outputting a display of“6041404126”. Your design should include a reset input controlled by pushbutton switch KEY1. Yourstate machine should reset on the rising edge of clk if KEY1 is pressed. Note KEY0 and KEY1 output a 1 when NOT pressed and a 0 when pressed (this is probably the opposite of what you would expect). Figure 1 shows the overall system you will build. 2 Lab Procedure Design a state machine in Verilog to implement the circuit as described above. A sample state diagram might be something like the one shown in Figure 2 and assuming you used the first five digits of your phone number and your phone number happens to be “604-827-4116”. The reset should be synchronous. This means that when the reset signal is asserted (set to logic 1), the state machine is reset on the next rising edge of the clock.
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