Andhra Loyola Project: FM0/Manchester Encoding, SOLS, Power Gating

This project, conducted at Andhra Loyola Institute of Engineering and Technology, India, focuses on FM0 and Manchester encoding using the SOLS (similarity oriented logic simplification) technique. The primary goal was to overcome limitations in VLSI design by implementing SOLS, clock gating, and power gating methodologies. The project aimed to reduce power consumption and improve efficiency in digital communication systems. The student's role involved researching encoding techniques, implementing FM0 encoding, and utilizing Xilinx ISE and Verilog HDL for design and simulation. The work involved the application of power gating and clock gating to reduce power dissipation and improve performance. The project successfully reduced area, delay, and power consumption, demonstrating the effectiveness of the proposed approach. The project also highlights the use of Xilinx ISE programming system and Verilog HDL for coding and simulation. The team collaborated to brainstorm and refine the project, ensuring accurate results and adherence to coding guidelines.

CE 1.1 Information of Project
Name of this Project: FM0 and Manchester Encoding using SOLS Technique with
Clock Gating and Power Gating Methods
Project’s Location: Andhra Loyola Institute of Engineering and Technology, India
Duration of the Project: Please fill
Organization Involved: Andhra Loyola Institute of Engineering and Technology,
India
Role as well as Designation during the work: Team Member of the work
CE 1.2 Background of this Project work
CE 1.2.1 Basic Characteristics of the Project
The codes of FM0 and Manchester are being utilized for reaching out to dc balance as
well as improve the delay, power and area. However, the respective coding assorted qualities
within these codes of FM0 and Manchester subsequently limit the major possibility for
styling a completely reutilized VLSI outline for all. In this project, I have implemented a
procedure called SOLS or similarity oriented logic simplification for the purpose of beating
this restriction. This specific system of SOLS eventually increases the rate of equipment
usage from 57.14 percent to 100 percent for the encodings of Manchester and FM0. This
particular proposed system for the work is being utilized for power reduction technique like
power gating methodology as well as clock gating methodology. I have even checked that the
clock gating methodology is needed for the purpose of reduction of the dynamic power
dissipation and clock signal. On the other hand, power gating methodology is being utilized
for reducing static power dissipation. I have not only added singularly to the totally reutilized

VLSI outline, but also have decreased the total area to 14.2% and power by 67.3% with two
methodologies. Hence, in the work, I had done FM0 and Manchester encoding with the help
of SOLS technique with two methods of power gating and clock gating.
CE 1.2.2 Developed Objectives for the project work
I had selected this specific research work since I always had ample interest different
encodings. I have known that these encodings are being utilized in communications for better
conversion of a message to the special form to ensure effective transmission. These distinct
methodologies are also being utilized in military for high security. Amongst different
methods, I had selected Manchester and FM0. During successful implementation of this
specific project, I even had to ensure that the resources are being optimized to a high level, so
that maximum efficiency is gained without much complexity. The few developed objectives
of the project are:
 To propose a system for using in better power reduction technique like power gating
and clock gating methodologies.
 To ensure that there is a reduction of power to 67.3% and delay by 33.3% with the
help of power gating and clock gating methodologies.
 To use Manchester and FM0 encoding techniques for executing the work
successfully.
 To complete designing of VLSI auxiliary with the help of SOLS technique for both
FM0 and Manchester encodings with the help of power gating and clock gating
methodologies.
 To utilize Xilinx14.7 ISE programming system in the venture and Verilog HDL for
composing the code.
 To ensure if the results are bringing out maximum effectiveness to my project.

CE 1.2.3 My working area in this project work
Being a significant team member, my chief area of work was to research about
different encoding techniques in the most effective manner. Since, this was the first time that
I was executing a work completely by myself, I had to ensure that the project outcome is
proper. We were total of 6 members in our project team and hence we decided to arrange a
brainstorming session regarding the selection of project topics. I suggested the project topic
related to encodings and then shared the idea with rest of the 5 members and our team
selected the topic without any complexity.
CE 1.2.4 Group of people Involved in Project
Figure 1: Group of people involved in the work
CE 1.2.5 My major responsibilities and duties throughout the work
To finish this work, my first duty was to accomplish the research work for different
encoding methodologies. I researched about various methods like NRZ, FM0, Miller and
finally Manchester. As, it was the 1st project that I was completing with team members, I

ensured that the results are accurate and would be providing proper and appropriate results.
As soon as I had completed my research work, I decided to start the work. One of my major
responsibilities was to execute FM0 encoding in the most effective manner, so that the
project provides accurate results, as compared to any other encoding method. I took proper
sample for the work and then completed the analysis, according to coding guidelines.
Moreover, both the techniques of power gating and clock gating are also used by me to make
sure that encoding is completed successfully.
CE 1.3 Distinct Activities in this Work
CE 1.3.1 Comprehending the most Basic Theories Used in this Project work
I had taken up theoretical understanding of electronics and communications
engineering for ensuring the project report would be appropriate and accurate. After
researching, I understood that the transition between higher and lower logic states represent
binary digits for the encoding methods. I even researched about the SOLS technique of
similarity oriented logic simplification for beating the restriction of VLSI outline. Different
encodings are being utilized for minimization of clock path, area, buffer size and delay. The
processes of encoding and decoding were being utilized in conversions of analog to digital
and digital to analog. There are three vital modules of a DSRC handset, which are
miniaturized scale chip, baseband process, and RF front end.
I had to complete FM0 encoding after focusing on different parameters and aspects.

Figure 2: FM0 Encoding
For each and every value of X, this FM0 code eventually consisted of 2 different
segments, which were one for the previous half cycle of CLK, A as well as the succeeding
half cycle of the CLK called B. I even estimated the coding standards for FM0, which was as
follows:
The waveform was also noted in this particular experiment.
Figure 3: FM0 Waveform
Although Manchester encoding was not in included in my section, I had to check the
results of this particular encoding technique.

Figure 4: Manchester Encoding
CE 1.3.2 My main Engineering skills or knowledge that are applied in the work
For completing the work, I had used my knowledge and skills of electronics and
communications engineering. My core knowledge of different encodings is being used here.
Moreover, I have also applied my information of power grating and clock grating techniques
as well as Xilinx test system.
CE 1.3.3 Execution of the work and main Tasks Completed in this work
I executed this work after considering few distinct aspects and parameters of FM0 and
Manchester encoding methods. For making the experiment a successful one, I checked if the
equipment architectures are being led properly. After following the coding guidelines of
FM0, this FSM of this specific method was appeared in the first state of S1 as well as the
state code 11 for A and B separately.

Figure 5: FSM of FM0
I even had checked the architectures of both the encoding techniques of Manchester
and FM0, so that better effectiveness is obtained eventually.
Figure 6: Architecture of FM0 and Manchester Encoding
To complete the work, I have used two distinct techniques of power gating and clock
gating. Accurate simulation results were gained and we were able to complete VLSI auxiliary
designing while SOLS technique for both the encodings. Moreover, to confirm the timing
investigation, I have used Xilinx test system.
CE 1.3.4 Identified issue with its solution
1.3.4.1 Issue Identified in this project

The main struggle that I faced was during comparison of the existing and proposed
parameters for this work. I checked that the gained results were not matching with the
expected results and we would be facing major issue due to it.
1.3.4.2 Accurate Solution to the identified Technical Difficulty
After again checking this struggle, I understood that I have to change the dynamic
power for rectifying my mistake and finally was able to do so.
Table 1: Comparison of different parameters
CE 1.3.5 Major Plan made to provide innovative and even creative works
I decided to analyse every aspect and feature that is required for the work. As a result,
the project came out with accurate results and I was able to complete within deadline and
budget.
CE 1.3.6 Work Collaborations
Being a part of the team, I decided to collaborate with my project leader as well as 5
other team members by taking their opinions as well as ideas. Moreover, we even researched
n scholarly articles for gaining maximum knowledge.

CE 1.4 Overall Reviewing of the Project
CE 1.4.1 Overview of this Project
I successfully executed this work for designing VLSI outline with SOLS technique
for both the encodings of Manchester and FM0. I have used two techniques of power grating
and clock grating. Moreover, Xilinx has been used to complete testing of the work.
CE 1.4.2 My Major Contribution to this work
As I was a responsible team member, I had to focus on my research work. My main
contribution was to complete FM0 encoding appropriately and also resolve the complexity
faced.