Computer Architecture Assignment: Binary Addresses

Added on - 28 May 2020

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Computer Architecture1The table below depicts the index bits, tag bits, block offset bits and hit/miss results of the threecache configurations:MemoryaddresssequenceBinaryaddress bitsTag bitsIndex bitsHit/MissC1C2C3C1C2C3C1C2C36000 00 110000001000214110 10 110110101100175101 01 111101011011214110 10 1101101011006000 00 11000000100084010 10 100010101100HH65010 00 001010000001HHH174101 01 11010101101064010 00 000010000000105011 01 00101101001185010 10 101010101101HH215110 10 111110101101In summary, the difference between C1, C2 and C2 are the block- offsets which affects the indexfield and though they are all of the same capacity, the tag field remains unchanged for C2 and C3C1: Index: (8 entries); byte offset: 1:0 (1 word/block)C2: Index: (8 entries); byte offset: 2:0 (2 word/block)C3: Index: (2 entries); byte offset: 1:0 (1 word/block)References
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