EE4363 Computer Architecture Homework: Caches, ISA, and Pipelining

This document contains solutions to a computer architecture homework assignment for the EE4363/CSci 4203 course. The assignment covers key concepts including Instruction Set Architecture (ISA), cache memory, and pipelining. Problem 1 delves into the intricacies of ISA, exploring register files, and the challenges in expanding the number of registers, with a focus on stack, accumulator, register-memory, and register-register architectures. Problem 2 examines cache performance through a series of memory access patterns, requiring analysis of cache hits and misses, and the contents of a cache. Problem 3 explores data dependencies in code, specifically identifying dependencies between instructions involving memory loads and stores. The solutions provide detailed explanations and answers to each problem, offering a comprehensive understanding of computer architecture principles. The document is a valuable resource for students studying computer organization and architecture.

Problem 1
Solution (a)
Solution (b)
Solution (c)
To begin with, not all processor models stop at 32 registers. Practically all RISC structures that uncover
32 registers in the guidance set really have 32 number registers and 32 coasting point registers (in this
way 64). (Drifting point "include" utilizes a register not quite the same as the number "include".) The
SPARC design has a register window. SPARC can just access 32 whole number registers one after
another, yet enlists work like stacks and can push and pop 16 new registers one after another. The
HP/Intel Itanium design uncovered 128 whole number and 128 coasting point enlists in guidance sets.
The entirety of the most recent GPUs from NVidia, AMD, Intel, ARM and Imagination Technologies
uncover countless registers to enlist documents. (I realize this is valid for the NVidia and Intel
engineering, however I don't think a lot about the AMD, ARM, and envision guidance sets, yet I think the
register record is additionally enormous.)
Second, the majority of the most recent chip execute register name changes to wipe out superfluous
serialization brought about by asset reuse, which can bring about a huge fundamental physical register
document (96, 128, or 192 registers on certain machines). This (and dynamic booking) requires the

compiler to produce an enormous number of extraordinary register names, while the scheduler must
give a bigger register record.
There are two reasons why it is hard to build the quantity of registers distributed in the guidance set. To
start with, you should have the option to determine a register identifier in every guidance. Since 32
registers require a 5-piece register specifier, 3-address guidelines (regular in RISC engineering) utilize 15
of the 32-guidance bits just to indicate the register. In the event that you increment this to 6 or 7 bits,
you have less space to indicate the opcode and constants. GPUs and Itanium have a lot more
noteworthy directions. Bigger guidelines are costly. Since more guidance memory must be utilized,
guidance store conduct isn't perfect.
The subsequent explanation is get to time. Bigger memory implies more slow access to information from
memory. (With respect to essential material science, since information is put away in two-dimensional
space, on the off chance that you store n bits, the normal separation to a specific piece is O(n-√).) The
register record is little. Multiport memory, and one of the impediments of expanding it, is that the
machine's clock should in the long run be delayed to oblige bigger register documents. This is typically a
misfortune for by and large execution.
Problem 2
Solution (a)
30 Miss
86 Miss
53 Miss
61 Miss
29 Miss
37 Miss
30 Miss
45 Miss
6 Miss
22 Miss
14 Miss
6 Miss
53 Miss
29 Miss
78 Miss
22 Miss

70 Hit
61 Miss
54 Miss
78 Miss
45 Miss
30 Hit
61 Hit
37 Miss
45 Miss
6 Miss
29 Miss
Solution (b)
Index 0000 0001 0010 0011 0100 0101 0110 0111
Content
s
M(17) M(19) M(4) M(5) M(6)
Index 1000 1001 1010 1011 1100 1101 1110 1111
Content
s
M(56) M(9) M(43)
Problem 3
Solution (a)
There are two data dependencies: on $6 between the sw and the add, and on $1 between the sw and
the lw.
Solution (b)

Solution (c)