Computer Organization

This study material covers topics related to computer organization such as conversions, circuit diagrams, and logic gates. It includes answers to questions on number conversions, minimized circuit diagrams, and Boolean algebra. The bibliography lists sources for further reading.

Running head: COMPUTER ARCHITECTURE
Computer Organization
Name of Student –
Name of University –
Author’s Note –

1COMPUTER ARCHITECTURE
Answer to Question 1
a) (152)x= (6A)16
 X2 + (5 * X1) + (2 * X0) = (6 * 161) + (10 * 160)
 X2 + 5X + 2 = 106
 X2 + 5X - 104 = 0
 X2 + 13X - 8X – 104 = 0
 X(X + 13) – 8(X + 13) = 0
 (X - 8) (X + 13) = 0
 X = 8 and X = -13
So, the value of X is 8
b) Conversions
1) BED16 to base 3
BED = (B * 162) + (E * 161) + (D * 160)
= 2816 + 224 + 13
=305310
(3053)10 =

2COMPUTER ARCHITECTURE
BED16 = (11012002)3
2) 3217 changing into 2-base
3217 = (3 * 72) + (2 * 71) + (1 * 70)
= (162)10
(162)10 =
(162)10 = (10100010)2
3) 1235 converting into octal representation

3COMPUTER ARCHITECTURE
(1235) = (2323)8
4) 21.218 converting into decimal representation
21.218 = (2 * 81) + (1 * 80). (2 * 8-1) + (1 * 7=8-2)
= 17 + 0.25 + 0.015625
= 17.265625
c) i) In a computer of 3 word size, one’s Complement lowest number = 100
In a computer of 3 word size, one’s Complement lowest number of word size 3 bit = 011
ii) In a computer of 3 word size, two’s Complement lowest number of word size 3 bit =
101
In a computer of 3 word size, two’s Complement lowest number of word size 3 bit = 011
iii) In a computer of 3 word size, signed Magnitude lowest number of word size 3 bit =
111
In a computer of 3 word size, signed Magnitude lowest number of word size 3 bit = 011

4COMPUTER ARCHITECTURE
Question 2
a) L.H.S
a b c d
0 0 0 1
0 1 0 1
1 0 0 1
1 1 1 0
R.H.S.
a b c d e
0 0 1 1 1
0 1 1 0 1
1 0 0 1 1
1 1 0 0 0

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From the above discussion, it can be stated that L.H.S. is equal to R.H.S.
b) Minimized Circuit Diagram
c) X’ + Y’ + XYZ’
= X’ + Y’ + (X’ + Y’ + Z)’ [From, De Morgan Law]
= (XY (X’ + Y’ + Z))’ [From, De Morgan Law]
= (XX’Y + XYY’ + XYZ)
= (0 + 0 + XYZ)
= (XYZ)’
= X’ + Y’ + Z’ [From, De Morgan Law]
[Hence, PROVED]

6COMPUTER ARCHITECTURE
Bibliography
Li, K., Ting, H. F., Foster, M. A., & Foster, A. C. (2016). High-speed all-optical NAND/AND
logic gates using four-wave mixing Bragg scattering. Optics letters, 41(14), 3320-3323.
Drake, C. (2015, August). Pyeda: Data structures and algorithms for electronic design
automation. In Proceedings of the 14th Python in Science Conference (SciPy 2015) (pp.
26-31).