FPGA Design with 7-Segment Displays

This practical assignment involves designing and implementing an FPGA circuit using Quartus II and VHDL to control 7-segment displays. The assignment is divided into two parts. Part 1 focuses on displaying characters on three 7-segment displays and rotating a three-character word across them. Part 2 extends the design to use all 7-segment displays on the DE-series board, displaying a three-letter word and rotating it across the displays while the rest show a blank character. The assignment requires using multiplexers, connecting switches, and testing the functionality on the FPGA board.

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Create a new Quartus II project for your circuit.
Part 1
Consider the circuit shown in Figure 7. It uses a two-bit wide 3-to-1 multiplexer to enable the selection of three
characters that are displayed on a 7-segment display. Using the 7-segment decoder from Part IV this circuit can
display the characters d, E, ‘blank’ and 0, 1, or 2 depending on your DE-series board. The character codes are
set according to Table 3 by using the switches SW5−0, and a specific character is selected for display by setting
the switches SW9−8.
An outline of the Verilog code that represents this circuit is provided in Figure 8. Note that we have used the
circuits from Parts III and IV as subcircuits in this code. You are to extend the code in Figure 8 so that it uses
three 7-segment displays rather than just one. You will need to use three instances of each of the subcircuits.
The purpose of your circuit is to display any word on the three 7-segment displays that is composed of the
characters in Table 3, and be able to rotate this word in a circular fashion across the displays when the
switches SW9−8 are toggled. As an example, if the displayed word is dE1, then your circuit should produce the
output patterns illustrated in Table 4.
Figure 7: A circuit that can select and display one of three characters.
SW9−8 Characters
00 d E 1
01 E 1 d
10 1 d E
Table 4: Rotating the word dE1 on three displays.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY part5 IS
PORT ( SW : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
LEDR : OUT STD_LOGIC_VECTOR(9 DOWNTO 0));
HEX0 : OUT STD_LOGIC_VECTOR(0 TO 6) );
END part5;
ARCHITECTURE Behavior OF part5 IS
COMPONENT mux_2bit_3to1
PORT ( S, U, V, W : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M : OUT STD_LOGIC_VECTOR(1 DOWNTO 0));
END COMPONENT;
COMPONENT char_7seg
PORT ( C : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
2
6
5
4
3
2
1
0
7
1 – 0SW
3 – 2SW
5 – 4SW
8SW
9SW
2
2
2
2
10
01
00
decoder
segment7-

Display : OUT STD_LOGIC_VECTOR(0 TO 6));
END COMPONENT;
SIGNAL M0 : STD_LOGIC_VECTOR(1 DOWNTO 0);
BEGIN
U0: mux_2bit_3to1 PORT MAP (SW(9 DOWNTO 8), SW(5 DOWNTO 4), SW(3 DOWNTO 2), SW(1
DOWNTO 0), M0); H0: char_7seg PORT MAP (M0, HEX0);
...
END Behavior;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
-- implements a 2-bit wide 3-to-1 multiplexer
ENTITY mux_2bit_3to1 IS
PORT ( S, U, V, W : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M : OUT STD_LOGIC_VECTOR(1 DOWNTO 0));
END mux_2bit_3to1;
ARCHITECTURE Behavior OF mux_2bit_3to1 IS
... code not shown
END Behavior;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY char_7seg IS
PORT ( C : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
Display : OUT STD_LOGIC_VECTOR(0 TO 6));
END char_7seg;
ARCHITECTURE Behavior OF char_7seg IS
... code not shown
END Behavior;
Figure 8: VHDL code for the circuit in Figure 7
Perform the following steps.
1. 1. Create a new Quartus II project for your circuit.
2. Include your VHDL entity in the Quartus II project. Connect the switches SW9−8 to the select inputs of
each of the three instances of the two-bit wide 3-to-1 multiplexers. Also connect SW5−0 to each instance
of the multiplexers as required to produce the patterns of characters shown in Table 2. Connect the SW
switches to the red lights LEDR, and connect the outputs of the three multiplexers to the 7-segment
displays HEX2, HEX1, and HEX0.
3. Include the required pin assignments for your DE-series board for all switches, LEDs, and 7-segment
displays. Compile the project.
3

Create a new Quartus II project for your circuit.
4. Download the compiled circuit into the FPGA chip. Test the functionality of the circuit by setting the
proper character codes on the switches SW5−0 and then toggling SW9−8 to observe the rotation of the
characters.
Part 2
Extend your design from Part V so that is uses all 7-segment displays on your DE-series board. board. Your
circuit needs to display a three letter word on three displays while the rest of the displays show a ’blank’. The
letters in the word are selected by three two-bit inputs as shown in Table 3. Also implement rotation of this
word from right-to-left as shown in Table 5 and Table 6. To do this, you will need to connect two-bit wide 6-to-
1 multiplexers to each of six 7-segment display decoders for the DE0-CV and DE1-SoC. For the DE2-115, you
will need to connect two-bit wide 8-to-1 multiplexers to each of the eight 7-segment display decoders. You will
need to use three select lines for each of the multiplexers: connect the select lines to switches SW9−7.
SW9−7 Character
pattern
000 d E 1
001 d E 1
010 d E 1
011 d E 1
100 E 1 d
101 1 d E
Table 5: Rotating the word dE1 on six displays.
SW9−7 Character
pattern
000 d E 2
001 d E 2
010 d E 2
011 d E 2
100 d E 2
101 d E 2
110 E 2 d
111 2 d E
Table 6: Rotating the word dE2 on eight displays.
Perform the following steps:
1. Create a new Quartus II project for your circuit.
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2. Include your VHDL entity in the Quartus II project. Connect the switches SW9−7 to the select inputs of
each instance of the multiplexers in your circuit. Also connect SW5−0 to each instance of the multiplexers
as required to produce the patterns of characters shown in Table 5 or Table 6 depending on your DE-
series board. (Hint: for some inputs of the multiplexers you will want to select the ‘blank’ character.)
Connect the outputs of your multiplexers to the 7-segment displays HEX5, ..., HEX0 of the DE0-CV and
DE1-SoC or HEX7, ..., HEX0 for the DE2-115.
3. Include the required pin assignments for your DE-series board for all switches, LEDs, and 7-segment
displays. Compile the project.
4. Download the compiled circuit into the FPGA chip. Test the functionality of the circuit by setting the
proper character codes on the switches SW5−0 and then toggling SW9−7 to observe the rotation of the
characters.
Copyright 2015 Altera Corporation.
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