Principles of Processor Operations

This presentation explores the principles of processor operations, including the role of registers, interrupt handling, and communication between the processor and peripherals. It also covers the creation of a low-level program with decision making and I/O operations. The impact of data bus and address bus width on processor performance and complexity is discussed. The presentation concludes with a summary of the key points.

Demonstrate the principles of
processor operations
Name of the student
Name of the University
Author Note

Table of content
• Introduction
• Processor registers in the fetch execute cycle
• Explaining function of interrupt handler
• How polling and interrupts are used to allow communication between processor
and peripherals
• Creation of a low-level program that includes decision making, branching and I/O
operations
• Impact of the width of the data bus and address bus on processor performance and
complexity.
• Conclusion
• References

Introduction
• CPU can be stated as the part of the
computer which executes the given program
instruction.
• It mainly comprises of three major
components that is ALU and register.
• The control unit aims to direct movement of
electrical signal in between the memory.
• Each of the set of instruction comprises of
microcode

Different processor registers in the fetch execute
cycle
There are large number of circuits being used
at the cycle phase that are
• Program counter
• Memory Address register
• Memory Buffer Register
• Current instruction register
• Accumulator
• Status register

Interrupt Handler
• An interrupt handler or interrupt
service routine can be defined as a
function which keeps the kernel
running with respect to specific
interrupt.
• Each of the device aims to generate
interrupt which is completely
associated to interrupt handler.
• Interrupt handler for any device is
considered to be part of device driver.

Features of Interrupt handler
There are generally two goals of
interrupt handler like
• Execution at a rapid rate
• Carrying out huge amount of work.

Explaining function of interrupt handler
• Processor come up with the order and magnitude which
are much faster in comparison to hardware.
• Interrupt handler or interrupt service routine (ISR) is the
function of the kernel. It is mainly needed for running in
response for the specific interrupt.
• Each of the device aim to generate interrupt which is a
part of interrupt handler.
• In the hardware the OS services are interrupted without
any kind of delay.

Polling and interrupts are used for communication
between processor and peripherals
• Both polling and interrupt are mainly used for allowing
communication in-between processor and peripherals.
• CPU does not stop what is being done and given to
peripheral attention.
• Polling can be defined as a method by programs can be
check the overall status of the peripheral devices.
• Interrupt is a method of signaling the CPU which is
needed by peripherals attention.

Creating of a low-level program that includes
decision making, branching and I/O operations
• Here a program has been developed
where a welcome message is being
displayed to user.
• The user can make a choice in
between the ticket that is normal or
monthly.

Decision making
• Here two kind of tickets are being offered to user
that is normal and monthly.
• An example has been shown where James name
has been entered. Where ticket is ready and
monthly charges stand at 30.50 dollars.

Decision making (Contd)
• If the user selects the option of monthly, then
he or she does not need to provide his or her
name.
• As soon as, the details are provided then user
need to pay the amount and collect it from
counter.

Decision making (Cond)
• The program will provide output if and only if
valid data is being provided to them.
• User need select either of the two option for getting
any output.

Impact data bus width and address bus effect on
processor performance and complexity
• Bandwidth or maximum output of front side of bus is
completely analyzed by product of product of width
and its data path.
• In addition, it also depends on clock frequency and
frequency of data transfer for performing it on per
cycle basis.
• The width of address bus aims to clearly define the
size of combination application for direct handling.
• 32-bit address bus is used for 4 GB of combined
memory.

Conclusion
The above slides help in concluding the fact that this presentation
is all principal of processor operation. CPU is defined as the
central processor or main processor in the whole electrical circuit
in the system. In the above slides, different processor register is
needed for fetching execution cycle. All the function of interrupt
handler has been provided. An idea has been provided with respect
to polling and interrupt for providing communication in between
peripherals and processor. In addition, a low level program has
been created which is needed for decision making.

References
• Giorgi, R. and Scionti, A., 2015. A scalable thread scheduling co-processor based
on data-flow principles. Future Generation Computer Systems, 53, pp.100-108.
• Benitez, J., 2016. Principles and modern applications of mass transfer
operations. John Wiley & Sons.
• Martyshkin, A.I., 2018. Basic operation principles of associate co-processor
module for specialized computer systems based on programmable logical integral
schemes. Journal of Fundamental and Applied Sciences, 10(6S), pp.1449-1463.
• Fuentes, J. and Scherson, I.D., 2018. Using Integrated Processor Graphics to
Accelerate Concurrent Data and Index Structures.