# ELEC41000 Electrical and Electronic Engineering

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Running head:DIGITAL ELECTRONICS LABORATORY ASSIGNMENT

DIGITAL ELECTRONICS LABORATORY ASSIGNMENT

Name of the Student

Name of the University

Author Note

DIGITAL ELECTRONICS LABORATORY ASSIGNMENT

Name of the Student

Name of the University

Author Note

DIGITAL ELECTRONICS LABORATORY ASSIGNMENT1

Abstract:

Digital electronics is one of the most important branch in electronics which deals with

different types of digital signals comprising of binary values (1 and 0). The logic operations

with binary values are performed using logic gates which are different types of logic circuits

that perform arithmetic or logic operations. In this laboratory the different types of logic

operations are performed and their equivalence is measure with Boolean algebra to have the

in depth concept of digital electronics.

Abstract:

Digital electronics is one of the most important branch in electronics which deals with

different types of digital signals comprising of binary values (1 and 0). The logic operations

with binary values are performed using logic gates which are different types of logic circuits

that perform arithmetic or logic operations. In this laboratory the different types of logic

operations are performed and their equivalence is measure with Boolean algebra to have the

in depth concept of digital electronics.

DIGITAL ELECTRONICS LABORATORY ASSIGNMENT2

Contents

Introduction:...............................................................................................................................4

Theory:.......................................................................................................................................4

Method:......................................................................................................................................5

Question 1a:............................................................................................................................5

Question 2a:............................................................................................................................7

Question 3a:..........................................................................................................................10

Question 3b:..........................................................................................................................12

Question 3c:..........................................................................................................................13

Question 4:............................................................................................................................15

Question 5a:..........................................................................................................................16

Conclusion:..............................................................................................................................18

References:...............................................................................................................................19

Contents

Introduction:...............................................................................................................................4

Theory:.......................................................................................................................................4

Method:......................................................................................................................................5

Question 1a:............................................................................................................................5

Question 2a:............................................................................................................................7

Question 3a:..........................................................................................................................10

Question 3b:..........................................................................................................................12

Question 3c:..........................................................................................................................13

Question 4:............................................................................................................................15

Question 5a:..........................................................................................................................16

Conclusion:..............................................................................................................................18

References:...............................................................................................................................19

DIGITAL ELECTRONICS LABORATORY ASSIGNMENT3

Introduction:

In particular different concepts and logic operations were understood by designing

and answering the 10 questions in the laboratory. For answering the questions the logic

circuits are designed in Multisim and the output is compared with the output that is obtained

using the Boolean expression (Hassanein 2018). The truth table is also formed for each logic

expression. Efforts has been made for clear and concise representation of logic circuits and

used concepts to reduce the paper length.

Theory:

The equivalence of two logic circuits can be obtained either by using the Boolean

algebraic reduction (where De-Morgan’s theorem is used most of the times) or by obtaining

the truth table of two Boolean expressions (Gensler 2017). Now, in case of large logic

expressions it is often practised to reduce the expression into smaller format i.e. either Sum of

Product (SOP) or Product of Sum (POS) form. Now, most effective method to reduce a logic

expression in SOP or POS form is to form a Karnaugh map which is much simpler than

Boolean algebraic reduction (Prasad 2017). Now, throughout this assignment various

questions are answered using the Boolean reduction technique, the K-Map reduction,

obtaining outputs from equivalent Multisim circuits (Smessaert and Demey 2016).

Furthermore, some more advanced logic circuits register (which performs multiple bit

storage) and counter (counting) is build using Multisim. Towards the end, specifically in the

last two questions, a Serial In Parallel Out (SIPO) and Parallel In Parallel Out (PIPO) register

and a modulo 10 ripple counter have been designed using the combinational logic circuits in

Multisim.

Introduction:

In particular different concepts and logic operations were understood by designing

and answering the 10 questions in the laboratory. For answering the questions the logic

circuits are designed in Multisim and the output is compared with the output that is obtained

using the Boolean expression (Hassanein 2018). The truth table is also formed for each logic

expression. Efforts has been made for clear and concise representation of logic circuits and

used concepts to reduce the paper length.

Theory:

The equivalence of two logic circuits can be obtained either by using the Boolean

algebraic reduction (where De-Morgan’s theorem is used most of the times) or by obtaining

the truth table of two Boolean expressions (Gensler 2017). Now, in case of large logic

expressions it is often practised to reduce the expression into smaller format i.e. either Sum of

Product (SOP) or Product of Sum (POS) form. Now, most effective method to reduce a logic

expression in SOP or POS form is to form a Karnaugh map which is much simpler than

Boolean algebraic reduction (Prasad 2017). Now, throughout this assignment various

questions are answered using the Boolean reduction technique, the K-Map reduction,

obtaining outputs from equivalent Multisim circuits (Smessaert and Demey 2016).

Furthermore, some more advanced logic circuits register (which performs multiple bit

storage) and counter (counting) is build using Multisim. Towards the end, specifically in the

last two questions, a Serial In Parallel Out (SIPO) and Parallel In Parallel Out (PIPO) register

and a modulo 10 ripple counter have been designed using the combinational logic circuits in

Multisim.

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