TESTBENCH CODE:Library IEEE;use IEEE.STD_LOGIC_1164.ALL;entity state_diag_tb is-- Port ( );end state_diag_tb;architecture Behavioral of state_diag_tb iscomponent state_diag is port(clk : instd_logic;C : instd_logic;reset : instd_logic;C_out : outstd_logic_vector(1 downto 0));end component;signal clk : STD_LOGIC := '0';signal rst : STD_LOGIC := '1';signal x1 : STD_LOGIC := '0';signal y1 : STD_LOGIC_VECTOR(1 downto 0);beginuut : state_diag port map(clk=>clk,reset => rst, C=>x1,C_out=>y1);clock : processbeginclk <= not clk after 10 ns;wait for 20 ns;end process;reset : process
beginrst <= not rst after 10 ns;wait for 200 ns;end process;input : processbeginx1 <= not x1 after 15 ns;wait for 30 ns;end process;end Behavioral;REPORT:oWaveformHere x1 input is variable C.
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