Document on Assignment Circuit

Added on - 13 Apr 2020

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AssignmentCircuit 1 – Simple 2 bit up/down counter with asynchronousreset.State Diagram:VHDL CODE:library IEEE;use IEEE.STD_LOGIC_1164.ALL;use ieee.std_logic_1164.all;entity state_diag isport(clk: instd_logic;C: instd_logic;reset: instd_logic;C_out : outstd_logic_vector(1 downto 0));end state_diag;architecture Behavioral of state_diag istype state_type is (s0, s1, s2, s3);signal state : state_type;beginprocess (clk, reset)
beginif reset = '1' thenstate <= s0;elsif (rising_edge(clk)) thencase state iswhen s0=>if C = '0' thenstate <= s1;elsestate <= s3;end if;when s1=>if C = '0' thenstate <= s2;elsestate <= s0;end if;when s2=>if C = '0' thenstate <= s3;elsestate <= s1;end if;when s3=>if C = '0' thenstate <= s0;elsestate <= s2;end if;end case;end if;end process;process (state, C)begincase state iswhen s0=>C_out <= "00";when s1=>C_out <= "01";when s2=>C_out <= "10";when s3=>C_out <= "11";end case;end process;end Behavioral;
TESTBENCH CODE:Library IEEE;use IEEE.STD_LOGIC_1164.ALL;entity state_diag_tb is-- Port ( );end state_diag_tb;architecture Behavioral of state_diag_tb iscomponent state_diag isport(clk: instd_logic;C: instd_logic;reset: instd_logic;C_out : outstd_logic_vector(1 downto 0));end component;signal clk : STD_LOGIC := '0';signal rst : STD_LOGIC := '1';signal x1 : STD_LOGIC := '0';signal y1 : STD_LOGIC_VECTOR(1 downto 0);beginuut : state_diag port map(clk=>clk,reset => rst, C=>x1,C_out=>y1);clock : processbeginclk <= not clk after 10 ns;wait for 20 ns;end process;reset : process
beginrst <= not rst after 10 ns;wait for 200 ns;end process;input : processbeginx1 <= not x1 after 15 ns;wait for 30 ns;end process;end Behavioral;REPORT:oWaveformHere x1 input is variable C.
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