Electronics Coding and Testing Content 2022

Electronics
Embedded system
Real-Time Filter Coding and Testing
Student Name –
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Contents
Introduction........................................................................................................... 3
Chapter 1: Background.......................................................................................... 4
1.1 Theory of TDL filter structure.......................................................................4
1.2 MACs and other computations needed.........................................................4
1.3 Theory of fixed-point saturation arithmetic..................................................4
1.4 Handling fractions in fixed-point arithmetic.................................................4
1.5 Theory of calculating timing in real-time programs......................................4
1.6 Standard input test signals: Impulse, Nyquist and step response................5
1.7 The PIC architecture and instruction set: its limitations...............................5
Chapter 2: Coding and design of filter...................................................................5
2.1 Explanations of real-time code.....................................................................5
2.2 Explanations of set-up code.........................................................................6
Chapter 3: Testing of software filter......................................................................7
3.1 Methods of testing........................................................................................ 7
3.2 Results of testing.......................................................................................... 7
The results obtained are shown in the Table above.....................................................8
3.3 Estimated timings of code in real-time loop.................................................8
3.4 Estimated maximum sampling rate achievable............................................8
Chapter 4: Performance enhancement using a different computer architecture...9
4.1 Discussion of processor architecture theory and performance.....................9
4.2 Performance Enhancement........................................................................10
Conclusion:.......................................................................................................... 10
Appendix:............................................................................................................ 10
References........................................................................................................... 13
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Introduction
A filter structure is provided for using and the number of bits for using for the filters
16-bit saturation logic arithmetic. Sign Extension, sign protection, n-bit arithmetic
handling, n-bit saturation logic need to be used. A code is written to implement the
filter structure given using 16-bit saturation logic arithmetic. Also, 2 binary fractional
bits ( ½ and ¼ ) are allowed. The input value x(t) is assumed to be a 8-bit signed
integer value which can have a value between -128 and 127. The worst case
number of instruction cycles that the real-time loop of the filter takes and the
maximum possible input sample rate for real-time processing is determined. It is tried
to minimise the worst case number of instruction cycles by coding the filter in the
most efficient way feasible.
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Chapter 1: Background
1.1 Theory of TDL filter structure
The TDL ( tapped delay line ) filter structure consists of delay lines with one or
more taps [1]. The delay line tap can be used for extracting a signal output from
a point in the delay line, can scale it and can sum with the different taps to get the
final output signal. If the simulation of several echoes has to be done from 1
source signal, then tapped delay line can be used. A TDL can be designed which
has a tap ( after every delay element ). It represents an FIR ( Finite Impulse
Response ) filter which is causal in nature [2].
1.2 MACs and other computations needed.
The multiply – accumulate circuit ( MAC ) helps in finding the product of 2
numbers and adds the result obtained with the accumulator. It is used many
times in the applications of digital signal processing. It is capable of performing 2
functions – multiplication and addition [3]. It can use signed or unsigned integers
as well as signed fixed – point fractional numbers as inputs. If faster operation is
needed, then fused MAC units may be used [4].
1.3 Theory of fixed-point saturation arithmetic.
In the representation of a number using fixed point, the number of digits is fixed
after the decimal point. It is helpful for the representation of fraction values ( using
the base 2 or 10 ). However, this may lead to loss of information. Also, there may
be the problem of overflow. The term ‘saturation arithmetic’ is used here to depict
that the operations ( like add and multiply ) have a limit on the range having a
minimum value and a maximum value [5].
1.4 Handling fractions in fixed-point arithmetic.
If the number of fractional bits is ‘x’, then in case of fixed point numbers, the
resolution is given by 1 / 2x [6].
1.5 Theory of calculating timing in real-time programs.
In case of a real time system, the response must be obtained within a given time
constraint. In case of a periodic task, the task needs to be repeated again and
again. In case of a dynamic task, the program runs in a sequential manner and
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