Embedded System Real-Time Filter Coding and Testing

This report details the design, coding, and testing of a real-time filter implemented on an embedded system, utilizing 16-bit saturation logic arithmetic and fixed-point representation. The report explores the theory of Tapped Delay Line (TDL) filters, MAC operations, and fixed-point arithmetic, including handling fractions and timing calculations for real-time programs. It covers the coding of the filter, including explanations of the real-time and set-up code, and the methods and results of testing. The report also analyzes the estimated timings, maximum sampling rate achievable, and discusses performance enhancement using different computer architectures, specifically the PIC microcontroller. The conclusion summarizes the findings, highlighting the filter's design and performance, as well as the limitations of the chosen architecture. An appendix provides the code, and a comprehensive list of references supports the analysis.

Electronics
Embedded system
Real-Time Filter Coding and Testing
Student Name –
Student ID -
1

Contents
Introduction...........................................................................................................................................3
Chapter 1: Background..........................................................................................................................4
1.1 Theory of TDL filter structure......................................................................................................4
1.2 MACs and other computations needed.......................................................................................4
1.3 Theory of fixed-point saturation arithmetic................................................................................4
1.4 Handling fractions in fixed-point arithmetic................................................................................4
1.5 Theory of calculating timing in real-time programs.....................................................................4
1.6 Standard input test signals: Impulse, Nyquist and step response................................................5
1.7 The PIC architecture and instruction set: its limitations..............................................................5
Chapter 2: Coding and design of filter...................................................................................................5
2.1 Explanations of real-time code....................................................................................................5
2.2 Explanations of set-up code.........................................................................................................6
Chapter 3: Testing of software filter......................................................................................................7
3.1 Methods of testing......................................................................................................................7
3.2 Results of testing.........................................................................................................................7
The results obtained are shown in the Table above..................................................................8
3.3 Estimated timings of code in real-time loop................................................................................8
3.4 Estimated maximum sampling rate achievable...........................................................................8
Chapter 4: Performance enhancement using a different computer architecture.................................9
4.1 Discussion of processor architecture theory and performance...................................................9
4.2 Performance Enhancement.......................................................................................................10
Conclusion:..........................................................................................................................................10
Appendix:............................................................................................................................................10
References...........................................................................................................................................13
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Introduction
A filter structure is provided for using and the number of bits for using for the filters
16-bit saturation logic arithmetic. Sign Extension, sign protection, n-bit arithmetic
handling, n-bit saturation logic need to be used. A code is written to implement the
filter structure given using 16-bit saturation logic arithmetic. Also, 2 binary fractional
bits ( ½ and ¼ ) are allowed. The input value x(t) is assumed to be a 8-bit signed
integer value which can have a value between -128 and 127. The worst case
number of instruction cycles that the real-time loop of the filter takes and the
maximum possible input sample rate for real-time processing is determined. It is tried
to minimise the worst case number of instruction cycles by coding the filter in the
most efficient way feasible.
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Chapter 1: Background
1.1 Theory of TDL filter structure
The TDL ( tapped delay line ) filter structure consists of delay lines with one or
more taps [1]. The delay line tap can be used for extracting a signal output from
a point in the delay line, can scale it and can sum with the different taps to get the
final output signal. If the simulation of several echoes has to be done from 1
source signal, then tapped delay line can be used. A TDL can be designed which
has a tap ( after every delay element ). It represents an FIR ( Finite Impulse
Response ) filter which is causal in nature [2].
1.2 MACs and other computations needed.
The multiply – accumulate circuit ( MAC ) helps in finding the product of 2
numbers and adds the result obtained with the accumulator. It is used many
times in the applications of digital signal processing. It is capable of performing 2
functions – multiplication and addition [3]. It can use signed or unsigned integers
as well as signed fixed – point fractional numbers as inputs. If faster operation is
needed, then fused MAC units may be used [4].
1.3 Theory of fixed-point saturation arithmetic.
In the representation of a number using fixed point, the number of digits is fixed
after the decimal point. It is helpful for the representation of fraction values ( using
the base 2 or 10 ). However, this may lead to loss of information. Also, there may
be the problem of overflow. The term ‘saturation arithmetic’ is used here to depict
that the operations ( like add and multiply ) have a limit on the range having a
minimum value and a maximum value [5].
1.4 Handling fractions in fixed-point arithmetic.
If the number of fractional bits is ‘x’, then in case of fixed point numbers, the
resolution is given by 1 / 2x [6].
1.5 Theory of calculating timing in real-time programs.
In case of a real time system, the response must be obtained within a given time
constraint. In case of a periodic task, the task needs to be repeated again and
again. In case of a dynamic task, the program runs in a sequential manner and
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when an event occurs, it invokes the program [7]. The several constraints may be
used to determine the timings.
1.6 Standard input test signals: Impulse, Nyquist and step response
For the purpose of testing the system, various standard input test signals can be
used. Some of them are described here. The impulse signal can be used which
consists of a non - zero value at t=0 and is zero elsewhere. The area under the
curve is 1 for the impulse function. A Nyquist function has negative and positive
values whose magnitude is equal. The step function has a value of zero for t < 0
and is 1 elsewhere [8].
The code is simulated for the following inputs:
o x(k) = {1,0,0,0,0,0,0,0,0……..)  impulse response
o x(k) = {1,1,1,1,1,1,1,1,1……}  step response
o x(k) = {-2,2,-2,2,-2,-2……..}  Nyquist response
o x(k) = {127,127,127 ………………….}
o x(k) = (-125, -125, -125 ……………..}
1.7 The PIC architecture and instruction set: its limitations
The Programmable Interface Controller ( PIC ) microcontroller consists of RAM,
Timers / Counters , flash memory, EEPROM, USART, I/O Ports, SSP, CCP, ADC,
PSP, Comparator, LCD, ICSP etc. It is an 8 – bit microcontroller. The PIC
microcontroller uses a RISC architecture having 35 instructions and due to this, the
length of the program may be large. There is only 1 accumulator available. The
program memory which is present cannot be accessed [ 9 ].
Chapter 2: Coding and design of filter
2.1 Explanations of real-time code
Here, the code is written using 16 bit arithmetic for the filter structure shown in Figure
3. The real time code is used to implement a filter structure whose output :
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Y ( k ) = [ 0.5 * x ( k – 1 ) + 2 * x ( k – 2 ) + 4 * x ( k – 3 ) + 0.25 * x ( k – 4 ) ]
The two’s complement saturation logic is used here. Initially, all the variables chosen
are cleared. If the value has to be divided by 2, then right shift operation is
performed. If the value has to be multiplied by 2, then left shift operation is
performed. If the value has to be divided by 4, then right shift operation is performed
twice. If the value has to be multiplied by 2, then left shift operation is performed
twice.
Figure 1 [9]
The Figure 1 shows the real time code in the running state.
2.2 Explanations of set-up code
The real-time fixed-point filter implementation is done efficiently on the micro-
controller platform. The timing calculation is done using the software. The
makeup and timing of the code affects the maximum real-time throughput of the
filter. The code is written for handling n-bit fixed point arithmetic using the micro-
controller architecture. The limitations of the architecture are discussed with
respect to the performance. The alternative microprocessor architectures are
studied. The alternative architectures like the TI controller, Blackfin controller or
PIC18 can help to reduce the number of cycles required [ 10 ].
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X(k-1)
X(k)
0.5
Y*(k) Y(k)
Chapter 3: Testing of software filter
3.1 Methods of testing
Filter implementation: Averaging Filter
In the averaging filter, the sum of the input and its delayed version is done. The sum
is then multiplied by the constant value 0.5. This gives the final result as output.
Hence, it finds the average value of the input and its delayed version.
Figure 2 [5]
The Figure 2 shows the
implementation of an
Averaging filter.
The testing can be done by
considering an initial input
and the noting the values at
successive time values.
3.2 Results of testing
Input / Output TABLE
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X(k)
K X(k) X(k-1) Y(k)
(ideal)
0 1 0 0.5
1 2 1 1.5
2 3 2 2.5
3 4 3 3.5
4 127 4 65.5
5 6 127 66.5
6 -128 6 -61
7 -127 -128 -127.5
8 8 -127 -59.5
9 2 8 5
10 2 2 2

The results obtained are shown in the Table above.
3.3 Estimated timings of code in real-time loop
The code which can be used for estimation is :
#include
clock_t s1,f1;
double t1;
s1 = clock();
do stuff;
f1 = clock(); t1 = (double) (f1 – s1) / (double) CLK_TCK
printf("Total = %f\n",t1);
The time obtained is 130 ms.
3.4 Estimated maximum sampling rate achievable
The time period of the fastest task = 10 ms.
Rate= 1/10 = 0.1 kHz
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Chapter 4: Performance enhancement using a different computer
architecture
4.1 Discussion of processor architecture theory and performance.
The parts like RAM, Timers / Counters , flash memory, EEPROM, USART, I/O Ports,
SSP, CCP, ADC, PSP, Comparator, LCD, ICSP etc are present in the
Programmable Interface Controller ( PIC ) microcontroller which is an 8 – bit
microcontroller. The PIC microcontroller uses a RISC architecture which has 35
instructions and because of this, the length of the program increases. There is only 1
accumulator present. The program memory which is present cannot be accessed
directly. But still the number of cycles needed can be decreased using the PIC
microcontroller and the optimization can be enhanced by improving the efficiency.
16 bit arithmetic logic
Filter Structure :
Figure 3 [8]
. b1 = ½, b2 = 2, b3 = 4, b4 = ¼, b0 = 0
It can be considered without fractional bits also.
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4.2 Performance Enhancement
The present system gives low optimization. Hence, PIC microcontroller can be used
to reduce the number of cycles required. This enhances the performance.
Conclusion:
Hence, the filter structure is designed for 16-bit saturation logic arithmetic and the
performance has been studied. The number of cycles needed can be decreased
using the PIC microcontroller and the optimization can be enhanced by improving
the efficiency. But there is a drawback that the PIC microcontroller uses a RISC
architecture which has 35 instructions and because of this, the length of the program
increases.
Appendix:
Code :
X(k)=x_k
Y(k)=y_K
Y*(k)=yx_k
X(k-1)=x_k_1
X(k-2)= x_k_2
X(k-3)= x_k_3
X(k-4)= x_k_4
; ##########################################
; A program to implement a filter structure [0.5*x(k-1)+2*x(k-2)+4*x(k-3)+0.25*x(k-4)]
; twos complement saturation logic used
; All input numbers assumed to be 2’s complement
; #########################################
list p=16f886 ; list directive to define processor
#include <p16f886.inc> ; processor specific variable definitions
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; '__CONFIG' directive is used to embed configuration data within .asm file.
; The labels following the directive are located in the respective .inc file.
; See respective data sheet for additional information on configuration word.
__CONFIG _CONFIG1, _LVP_OFF & _FCMEN_ON & _IESO_OFF & _BOR_OFF
& _CPD_OFF & _CP_OFF & _MCLRE_OFF & _PWRTE_ON & _WDT_OFF
& _INTRC_OSC_NOCLKOUT
__CONFIG _CONFIG2, _WRT_OFF & _BOR21V
; #########################################
; Label declarations
; note all locations in page 0 after 0x0b available as general RAM locations
x_k equ 0x20 ;label for x(k)
x_k_1 equ 0x21 ;label for x(k-1)
yx_k equ 0x22 ;labelfor y*(k)
y_k equ 0x23 ;labelfor y(k)
sign equ 0x07 ;bit position of sign
;**********************************************************************
ORG 0x000 ; processor reset vector
nop
gotomain_start ; go to beginning of program
ORG 0x004 ; interrupt vector location
goto ISR_START
; #########################################
; overflow detection and saturation sub-routine
; for simulation purposes only
overflow btfss x_k,sign ; test for sign of input data
goto positive
btfss x_k_1,sign ; test for possibility of negative overflow
goto test_end
btfsc y_k,sign ; test for negative overflow
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goto test_end
movlw 0x80
movwf y_k ;saturate result register to -128
goto test_end
positive btfsc x_k_1,sign ; test for positive overflow possibility
goto test_end
btfss y_k,sign ; test for positive overflow
goto test_end
movlw d'127' ; saturate result to +ve (127)
movwf y_k
test_end return
; ############### main algorithm ################
main_start
; initialise values
clrf x_k ;x(-1)=0
clrf x_k_1 ;x(k-1)=0
clrf x_k_2 ;x(k-2)=0
clrf x_k_3 ;x(k-3)=0
clrf x_k_4 ;x(k-4)=0
clrf y_k ;y(-1)=0
clrf yx_k ;y*(-1)=0
clrf ADRESH ; simulation purposes
BSF ADCON0, ADON ; for simulation purposes
next_input nop ; do nothing, wait for simulator to put next value
into x(k)
BSF ADCON0,GO ; for simulation purposes, grab next value for
x(k)
movf ADRESH,0
movwf x_k
movf x_k_1,0 ; w=x(k-1)
addwf x_k,0 ; w=x(k)+x(k-1)
movwf y_k ; y(k)=x*k)+x(k-1)
call overflow ; check for negative and positive overflow
movf y_k,0
movwf yx_k
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