Digital Design Project: Elevator Controller on DE1-SoC Board

This project details the design and implementation of a four-floor elevator controller using Verilog code on a DE1-SoC FPGA board. The project begins with the creation of an elevator circuit using logic gates, encoders, and decoders, which is then tested. Subsequently, Verilog code is written based on the tested circuit. The report includes an introduction to the elevator system, an overview of FPGA architecture, and the control flow of an elevator. It further details the design process, including sample inputs, an event list, and the implementation of priority encoders for both upward and downward elevator movements. The Verilog code is designed to control the elevator's movement based on user requests from inside and outside the elevator, taking into account the priority of requests and the current position of the elevator. The project demonstrates the application of digital design principles in creating a practical system using an FPGA, including the creation of truth tables, and logic equations, culminating in a fully functional elevator control system implemented in Verilog.

Electrical Digital Verilog FPGA

ABSTRACT
The purpose of this project is to create an elevator controller for four floors of a building.
This has to be build according to the FPGA - DE1 SoC board. First step is to create a circuit
using logic gates, encoder, decoders and integrated chips to create an elevator controller. Then
the circuit was tested. The Verilog code was written after testing of the designed circuit of the
elevator is completed.
1

Table of Contents
1. INTRODUCTION.............................................................................................................................3
2. ARCHITECTURE OF FPGA..........................................................................................................3
3. CONTROL FLOW OF AN ELEVATOR........................................................................................5
4. DESIGN OF ELEVATOR PROCESS.............................................................................................6
5. CONCLUSION................................................................................................................................11
REFERENCES........................................................................................................................................12
2

1. INTRODUCTION
The four floor elevator consists of inputs from inside of the elevator as well as the inputs
from the outside of the elevator. There are four floor buttons inside the elevator and up and down
buttons available in the outside of the floor except ground floor and third floor. Ground floor
only has up button and third floor only has down button. The direction of the elevator is
determined at an instant and after that priority of all the events is determined using priority
encoder for both upward and downward direction. The outputs of the encoder are given to the
decoder and then the decoder outputs are used to find the position of the elevator by forming
logic equations. Using these logic equations of direction, priority of events for both upward and
downward direction and position of the elevator for both upward and downward direction the
circuit for four floor elevator is designed.
1. ARCHITECTURE OF FPGA
FPGA is also known as Field Programmable Gate Array which comes under user
programmable digital devices called Programmable Logic Devices (PLD’s) (Mehmet and Ayhan
1658-1669).In PLD’s, Field Programmable Gate Array provide the next generation. In the name
of FPGA, the word ‘Field’ refers to the ability of the gate array to be programmed for a
particular function by the user. A PLD enables the user to configure it in many ways, enabling
the implementation of various digital logic functions, of varying sizes and complexities. It is an
integrated circuit ("Intel® Fpgas and Programmable Devices - Intel® FPGA"). Programmable
logic devices classified into four categories. They are mentioned below
1. Simple programmable logic devices (SPLD)
(i) Programmable array logic (PAL): A Programmable array logic is an IC and it contains a
fixed OR plane followed by a programmable AND plane.
(ii) Programmable logic array (PLA): A PLA is an integrated circuit. A PLA contains two levels
of programmable logic. They are an AND plane and an OR plane.
3

2. Field Programmable Gate Array (FPGA)
3. Complex Programmable Logic Device (CPLD)
FPGA (Field Programmable Gate Array) has the below mentioned components:
1. Programmable Logic blocks
2. Input output blocks(IOB)
3. Interconnection Resources
Figure 1Schematic diagram of FPGA
The above diagram shows the schematic diagram of FPGA. FPGA consists of
Programmable logic blocks which is also called as Configurable Logic Block (CLB) in the
Xilinx family of FPGA (Ibrahimy 466-477).
4

2. CONTROL FLOW OF AN ELEVATOR
Figure 2 Control flow of an Elevator
Based on the flow of the traffic light controller the elevator controlled is designed
Assume, initially elevator is in a rest position. Controller in the elevator continuously checks
inputs or requests which are given by users (Ge 033014). When user press a button for down or
up request, the controller takes corresponding actions. If it is up request, the controller prepares
elevator to move up. That means it closes the door of the elevator and starting to move up.
Likewise, when controller gets down request form the user it Sensors are fixed in each floor and
it senses the position of the elevator (Mohammed and Ali 780-783). When control system gets
input from the sensor it sends stop signal to the elevator. Then the elevator stopped and door of
the elevator is opened. The elevator door is at open position until it gets user input for closing
door. Then controller takes action according to the user request.
5

3. DESIGN OF ELEVATOR PROCESS
Sample Inputs
The inputs for the elevator is given as the sample inputs in the below table. In this table,
the User’s position, Symbol and Information request.
Table 1 Sample Input for Elevator
Users position Symbol Information request
Inside the elevator GF Ground floor
Inside the elevator 1F First floor
Inside the elevator 2F Second floor
Inside the elevator 3F Third Floor
Outside the elevator GU Upwards Ground floor
Outside the elevator 1D Downwards from first floor
Outside the elevator 1U Upwards from first floor
Outside the elevator 2D Downwards from Second
floor
6

Outside the elevator 2U Upwards from second floor
Outside the elevator 3D Downwards from Third floor
Events list of the elevator:
The below table shows the list of events takes place in the elevator. In this table, the
elevator position, Symbol and the Event are described in each floor.
Table 2 Events list of the Elevator
Elevator Position Symbol Event
At Ground Floor Status- Ground 1F ,2F ,3F – These floors are
pressed from Inside
1D,1U,2D,2U,3D –These are
pressed from outside
At First Floor Status – 1F GF,2F,3F – Pressed from
Inside
GU,2U,2D,3D – Pressed
from Outside
At Second Floor Status – 2F GF, 1F, 3F – Pressed from
Inside
GU,1U,1D,3D – Pressed
7

from Outside
At Third Floor Status – 3F GF,1F,2F – Pressed from
Inside
GU, 1U, 1D, 2U, 2D –
Pressed from Outside.
Priority Encoder
Priority encoder produces the output regarding to the priority of one or more same input.
In elevator controller it is used for the selection of floors in the movement direction. Here two
directions are considered. One is upward and another one is downward.
The priority encoder for the upward direction movement of the lift is given below. It uses
10 to 4 priority encoder. It means it consists of 10 inputs and 4 outputs. The inputs are
represented in the floors. The outputs are represented as Q0, Q1, Q2 and Q3. In the below table,
D indicates Down, U indicates Up, F indicates Floor. G indicates Ground.
Table 3 Priority encoder table for upward movement of Elevator
1D 2D 3D 3F 2U 2F 1U 1F GU GF Q3 Q2 Q1 Q0
X X X X X X X X X 1 1 1 1 1
X X X X X X X X 1 0 1 1 1 0
X X X X X X X 1 0 0 1 1 0 1
8

X X X X X X 1 0 0 0 1 1 0 0
X X X X X 1 0 0 0 0 1 0 1 1
X X X X 1 0 0 0 0 0 1 0 1 0
X X X 1 0 0 0 0 0 0 1 0 0 1
X X 1 0 0 0 0 0 0 0 1 0 0 0
X 1 0 0 0 0 0 0 0 0 0 1 1 1
1 0 0 0 0 0 0 0 0 0 0 1 1 0
The output equation of the above table is given below,
Q3=GF+GU.(GF’)+[(1F+1U.(1F’)).(GU’).(GF’)]+[(2F+2U.(2F’)).(1U’)(1F’)(GU’)(GF’)]
+[(3F+3D.(3F’))(2U’)(2F’)(1U’)(1F’)(GU’)(GF’)]+[(2D+1D.(2D’))(3D’)(3F’)(2U’)(2F’)(1U’)
(1F’)(GU’)(GF’)]
Q2=GF+GU.(GF’)+[(1F+1U(1F’)).(GU’)(GF’)]+[(2D+1D.(2D’)).(3D’)(3F’)(2U’)(2F’)(1U’)
(1F’)(GU’)(GF’)]
Q1=GF+GU.(GF’)+[(2F+2U(2F’)).(1U’)(1F’)(GU’)(GF’)]+[(2D+(1D+2D’)).(3D’)(3F’)(2U’)
(2F’)(1U’)(1F’)(GU’)(GF’)]
Q0=GF+1F.(GU’)(GF’)+[(2F+3F(2U’)(2F’)).(1U’)(1F’)(GU’)(GF’)]+[2D(3D’)(3F’)(2U’)(2F’)
(1U’)(1F’)(GU’)(GF’)]
9

The downward direction uses 8 to 3 encoder. This means it consists of 8 input and 3
output. Here the inputs are represented as floors. The output are represented as Q0, Q1, and Q2.
Table 4Priority encoder table for downward movement of Elevator
2U 1U GU GF 1D 1F 2D 2F Q2 Q1 Q0
X X X X X X X 1 1 1 1
X X X X X X 1 0 1 1 0
X X X X X 1 0 0 1 0 1
X X X X 1 0 0 0 1 0 0
X X X 1 0 0 0 0 0 1 1
X X 1 0 0 0 0 0 0 1 0
X 1 0 0 0 0 0 0 0 0 1
1 0 0 0 0 0 0 0 0 0 0
The output equation for the downward direction of the elevator is given below,
Q2 = 2F + 2F’ [2D +2D’ (1F+1D.1F’)]
10

Q1 = 2F + 2F’ [2D+1D’.1F’.2D’ (GF+GU.G’F’)]
Q0 = 2F + 2D’. 2F’ [1F + 1D’.1F’. (GF + 1U. G’U’. G’E’)]
4. CONCLUSION
In this project, the verilog code for FPGA designed circuit for elevator is designed. Then
the circuit design for the elevator circuit using the encoder’s truth table was implemented.
11