Design and Implementation of Intelligent Gate Controllers

This assignment focuses on designing and implementing intelligent gate controllers using microcontrollers. It involves researching and presenting a PIC-based model for such systems, as well as exploring related studies and applications in various fields. The objective is to create an efficient and effective gate control system utilizing microcontrollers, which can be used in industrial and medical settings. Research papers from 2013 to 2015 are referenced, highlighting advancements and developments in this area.

Running head: EMBEDDED SYSTEM DESIGN
Embedded System Design
[Name of the Student]
[Name of the University]
[Author note]

1EMBEDDED SYSTEM DESIGN
Table of Contents
Introduction:....................................................................................................................................2
Discussion:.......................................................................................................................................3
PIC16F84A..................................................................................................................................3
Instruction set of PIC16F84A:.................................................................................................5
Pin diagram of PIC16F84A:....................................................................................................6
ATMEGA328P............................................................................................................................7
Instruction set of ATMEGA328P overview:...........................................................................8
BIT assignments of ATMEGA328P......................................................................................12
Pin diagram of ATMEGA328P:............................................................................................14
ATMEL89C51...........................................................................................................................15
Block diagram of ATMEL 89C51.........................................................................................17
Pin diagram of ATMEL89C51:.............................................................................................19
Instruction set of ATMEL 89C51:.........................................................................................19
Summary of comparison:...............................................................................................................26
Conclusion:....................................................................................................................................27
References:....................................................................................................................................29

2EMBEDDED SYSTEM DESIGN
Introduction:
Microcontroller or MCU generally refers to the small computer that present on a small
integrated circuit. According to the modern terminology it can be stated that MCU is almost
similar to a system on a chip but it is less sophisticated (Mouha et al. 2014). MCU can be one of
the components of SoC or System on a Chip. A MCU is divided in several parts and this might
include one or more CPUs, associated with a memory and peripherals for input and output. MCU
are generally designed for the embedded applications in contrast to the microprocessors that are
used in the personal computers and any other general purpose applications which consists of the
various discrete chips (Pöppelmann Oder and Güneysu 2015). This report generally compares
the three microcontroller with respect to their Architecture, Instruction sets, Families, Memory,
Peripherals, Speed, Cost, Development tools and Applications.

3EMBEDDED SYSTEM DESIGN
Discussion:
PIC16F84A
Fig 1: Architecture of PIC16F84A
PIC16F84A is an 18-pin enhanced Flash/EEPROM 8-Bit microcontroller paving an RISC
architecture. The basic block diagram of the PIC16F84 microcontroller is given below:

4EMBEDDED SYSTEM DESIGN
Fig 2: Block diagram of PIC16F84A
Program Memory (FLASH): This is used for the purpose of storing a written program. This is
due to the fact that the memory which is made using the FLASH technology can be cleared as
well as programmed more than once (Liu and Großschädl 2014). This in turn makes this type of
microcontrollers very much suitable for the development of a device.
EEROM: This is generally used for the purpose of storing the vital information so as to protect
the data from getting lost whenever there is a sudden stop in the power supply.
RAM: This is the data memory which is generally used during the process of execution. The
RAM also stores all the inter-results as well as the temporary data generated during run-time
(Arends et al. 2017).
PORT A and PORT B: Both of this port act as the physical connection between the external
world and the microcontroller (Lee Kim and Park 2013). Port A consists of 5 pin whereas the
port B consists of 8 pins.
FREE-RUN TIMER: This is the 8-bit register which is present inside the microcontroller which
works independently irrespective of the program (Adewuyi Okelola and Jemilehin 2013). The

5EMBEDDED SYSTEM DESIGN
value gets incremented after each fourth clock of the oscillator and continue to get incremented
unless and until the maximum value is reached i.e. 255. After reaching the maximum value it
again starts from Zero.
CENTRAL PROCESSING UNIT: This is responsible for connecting the different elements
present at the other blocks of the microcontroller (Bates 2013). It is responsible for coordinating
the works of the different blocks along with executing the user programs.
Instruction set of PIC16F84A:
Mnemonics & Operands Description
ADDWF f,d Add contents of W-register and f and store the contents in the
specified address(d)
ANDWF f,d AND the contents of W-register and f and store the contents in
the specified address(d)
CLRF f Clear the contents of f
CLRW Clear the contents of W-register
COMF f,d Compliments the contents of f and stores the result in
d(destination)
DECF f,d Decrement f and store the result in the destination(d)
DECFSZ f,d Decrement f, skip if zero
INCF f,d Increment f and store the result in destination (d)
INCFSZ f,d Increment f, skip if zero
IORWF f,d Incluse OR contents of W-register with contents of f and store
the result in destination(d)
MOVF f,d move the contents of f to destination(d)
MOVWF f Move the contents of W-register to fM
NOP No operation (remains quiet for one cycle)
RLF f,d Rotate left f through carry
RRF f,d Rotate right f through carry
SUBWF f,d Subtract contents of W-register from f

6EMBEDDED SYSTEM DESIGN
SWAPF f,d Swaps nibbles in f
XORWF f,d Exclusive OR contents of W-register with f
Pin diagram of PIC16F84A:

7EMBEDDED SYSTEM DESIGN
ATMEGA328P
Fig 3: Architecture of ATMEGA328P
ATmega328P is a microchip having high performance along with a low power design.
This is a 32K 8-bit microcontroller which is based upon the AVR architecture. In a single clock
many of the instructions are executed which initially provides a throughput of around 20 MIPS at
a frequency of 20 MHz. This is an 8-bit microcontroller which is having an advanced RISC
architecture (Mellis et al. 2013). There are 131 instruction and most of this instructions are
executed in a single clock cycle and has a throughput of about 20 MIPS at 20 MHz. there are
32X8 registers in working state.
MEMORY: This microprocessor includes a 32 KB programmable FLASH, 1KB EPROM, and 2
KB SRAM. Along with this there is also 10,000 cycles for erase and write in FLASH and
100,000 cycle for the EEPROM. Along with this there is also an optional boot loader associated
with lock bits and a programming lock for the security of the software (Sarkar and Chowdhury
2015).

8EMBEDDED SYSTEM DESIGN
INPUT/OUTPUT PACKAGES: This microcontroller consists of 23 programmable
input/output lines and have a 28 pin PDIP package. This microcontroller operates at a voltage of
1.8-5.5 Volts and -400C to 850 C (Chang et al. 2013).
Instruction set of ATMEGA328P overview:
1
5
1
4
1
3
1
2
1
1
1
0 9 8 7 6 5 4 3 2 1 0
Instruction
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NOP
0 0 0 0 0 0 0 1 D D D D R R R R MOVW Rd,Rr Move register pair
0 0 0 0 0 0 1 0 d d d d r r r r MULS Rd,Rr
0 0 0 0 0 0 1 1 0 d d d 0 r r r MULSU Rd,Rr
0 0 0 0 0 0 1 1 0 d d d 1 r r r FMUL Rd,Rr
0 0 0 0 0 0 1 1 1 d d d u r r r FMULS(U) Rd,Rr
0 0 opcode r d d d d d r r r r 2-operand instructions
0 0 0 c̅y̅ 0 1 r d d d d d r r r r CPC/CP Rd,Rr
0 0 0 c̅y̅ 1 0 r d d d d d r r r r SBC/SUB Rd,Rr
0 0 0 cy 1 r d d d d d d r r r r ADD/ADC Rd,Rr (LSL/ROL Rd
when Rd=Rr)
0 0 0 1 0 0 r d d d d d r r r r CPSE Rd,Rr

9EMBEDDED SYSTEM DESIGN
0 0 1 0 0 0 r d d d d d r r r r AND Rd,Rr
0 0 1 0 0 1 r d d d d d r r r r EOR Rd,Rr
0 0 1 0 1 0 r d d d d d r r r r OR Rd,Rr
0 0 1 0 1 1 r d d d d d r r r r MOV Rd,Rr
0 0 1 1 K K K K d d d d K K K K CPI Rd,K
0 1 opc K K K K d d d d K k K K Register-immediate operations
0 1 0 c̅y̅ K K K K d d d d K K K K SBCI/SUBI Rd,K
0 1 1 0 K K K K d d d d K K K K ORI Rd,K
SBR Rd,K
0 1 1 1 K K K K d d d d K K K K ANDI Rd,K
CBR Rd,K
1 0 k 0 k k s d d d d d y k k k LDD/STD through Z+k or Y+k
1 0 0 1 0 0 s d d d d d opcode Load/store operations
1 0 0 1 0 0 s d d d d d 0 0 0 0 LDS rd,i/STS i,rd
16-Bit immediate SRAM address i
1 0 0 1 0 0 s d d d d d y 0 0 1 LD/ST Rd through Z+/Y+
1 0 0 1 0 0 s d d d d d y 0 1 0 LD/ST Rd through −Z/−Y
1 0 0 1 0 0 0 d d d d d 0 1 q 0 LPM/ELPM Rd,Z
1 0 0 1 0 0 0 d d d d d 0 1 q 1 LPM/ELPM Rd,Z+

10EMBEDDED SYSTEM DESIGN
1 0 0 1 0 0 1 d d d d d 0 1 0 0 XCH Z,Rd
1 0 0 1 0 0 1 d d d d d 0 1 0 1 LAS Z,Rd
1 0 0 1 0 0 1 d d d d d 0 1 1 0 LAC Z,Rd
1 0 0 1 0 0 1 d d d d d 0 1 1 1 LAT Z,Rd
1 0 0 1 0 0 s d d d d d 1 1 0 0 LD/ST Rd through X
1 0 0 1 0 0 s d d d d d 1 1 0 1 LD/ST Rd through X+
1 0 0 1 0 0 s d d d d d 1 1 1 0 LD/ST Rd through −X
1 0 0 1 0 0 s d d d d d 1 1 1 1 POP/PUSH Rd
1 0 0 1 0 1 0 d d d d d 0 opcode One-operand instructions:
1 0 0 1 0 1 0 d d d d d 0 0 0 0 COM Rd
1 0 0 1 0 1 0 d d d d d 0 0 0 1 NEG Rd
1 0 0 1 0 1 0 d d d d d 0 0 1 0 SWAP Rd
1 0 0 1 0 1 0 d d d d d 0 0 1 1 INC Rd
1 0 0 1 0 1 0 d d d d d 0 1 0 0 (reserved)
1 0 0 1 0 1 0 d d d d d 0 1 0 1 ASR Rd
1 0 0 1 0 1 0 d d d d d 0 1 1 0 LSR Rd
1 0 0 1 0 1 0 d d d d d 0 1 1 1 ROR Rd

11EMBEDDED SYSTEM DESIGN
1 0 0 1 0 1 0 0 B̅ b b b 1 0 0 0 SEx/CLx Status register clear/set bit
1 0 0 1 0 1 0 1 opcode 1 0 0 0 Zero-operand instructions
1 0 0 1 0 1 0 1 0 0 0 0 1 0 0 0 RET
1 0 0 1 0 1 0 1 0 0 0 1 1 0 0 0 RETI
1 0 0 1 0 1 0 1 0 0 1 x 1 0 0 0 (reserved)
1 0 0 1 0 1 0 1 0 1 x x 1 0 0 0 (reserved)
1 0 0 1 0 1 0 1 1 0 0 0 1 0 0 0 SLEEP
1 0 0 1 0 1 0 1 1 0 0 1 1 0 0 0 BREAK
1 0 0 1 0 1 0 1 1 0 1 0 1 0 0 0 WDR
1 0 0 1 0 1 0 1 1 0 1 1 1 0 0 0 (reserved)
1 0 0 1 0 1 0 1 1 1 0 q 1 0 0 0 LPM/ELPM
1 0 0 1 0 1 0 1 1 1 1 0 1 0 0 0 SPM
1 0 0 1 0 1 0 1 1 1 1 1 1 0 0 0 SPM Z+
1 0 0 1 0 1 0 c 0 0 0 e 1 0 0 1 Indirect jump/call to Z or EIND:Z
1 0 0 1 0 1 0 d d d d d 1 0 1 0 DEC Rd
1 0 0 1 0 1 0 0 k k k k 1 0 1 1 DES round k
1 0 0 1 0 1 0 k k k k k 1 1 c k JMP/CALL abs22

12EMBEDDED SYSTEM DESIGN
k k k k k k k k k k k k k k k k
1 0 0 1 0 1 1 0 k k p p k k k k ADIW Rp,uimm6
1 0 0 1 0 1 1 1 k k p p k k k k SBIW Rp,uimm6
1 0 0 1 1 0 B 0 a a a a a b b b CBI/SBI a,b (clear/set I/O bit)
1 0 0 1 1 0 B 1 a a a a a b b b SBIC/SBIS a,b (I/O bit test)
1 0 0 1 1 1 r d d d d d r r r r MUL, unsigned: R1:R0 = Rr × Rd
1 0 1 1 s a a d d d d d a a a a IN/OUT to I/O space
1 1 0 c 12 bit signed offset RJMP/RCALL to PC + simm12
1 1 1 0 K K K K d d d d K K K K LDI Rd,K
1 1 1 1 0 B̅ 7-bit signed offset b b b Conditional branch on status
register bit
1 1 1 1 1 0 s d d d d d 0 b b b BLD/BST register bit to STATUS.T
1 1 1 1 1 1 B d d d d d 0 b b b SBRC/SBRS skip if register bit
equals B
1 1 1 1 1 x x d d d d d 1 b b b (reserved)
.
BIT assignments of ATMEGA328P
Code Description

13EMBEDDED SYSTEM DESIGN
rrrrr Source register
rrrr Source register (R16–R31)
rrr Source register (R16–R23)
RRRR Source register pair (R1:R0–R31:R30)
ddddd Destination register
dddd Destination register (R16–R31)
ddd Destination register (R16–R23)
DDDD Destination register pair (R1:R0–R31:R30)
pp Register pair, W, X, Y or Z
Y Y/Z register pair bit (0=Z, 1=Y)
u FMUL(S(U)) signed with 0=signed or
1 Unsigned
s Store/load bit (0=load, 1=store)
c Call/jump (0=jump, 1=call)
cy With carry (0=without carry, 1=with carry)
e Extend indirect jump/call address with EIND
(0=0:Z, 1=EIND:Z)
q Extend program memory address with
RAMPZ (0=0:Z, 1=RAMPZ:Z)
aaaaaa I/O space address

14EMBEDDED SYSTEM DESIGN
aaaaa I/O space address (first 32 only)
bbb Bit number (0–7)
B Bit value (0 or 1)
kkkk 4-bit unsigned constant (DES opcode)
kkkkkk = 6-bit unsigned constant
KKKKKKKK 8-bit constant
Pin diagram of ATMEGA328P:

15EMBEDDED SYSTEM DESIGN
ATMEL89C51
Fig 4: Architecture of ATMEL89C51
ATMEL 89C51 is an 8-bit microcontroller which belongs to the Atmel’s 8051 family.
This microcontroller consists of a 4KB FLASH programmable and erasable read only memory or
PEROM along with a 128 byte of RAM (Kumar et al. 2013). This microcontrollers can be erased
and program to a maximum of 100 times. This microcontroller consists of 40 pins where the
ports are designated as P1, P2, P3 and P0. All this ports are of 8-bit and are bi-directional in nature
which means that this ports can be used as input as well as output ports. The ports P1, P2 and P3
have internal pull-ups but P0 needs external pull-ups (Parai Das and Das 2013). This

16EMBEDDED SYSTEM DESIGN
microcontroller is manufactured by making use of the “high-density non-volatile memory
technology” of Atmel (Srinivasan and Vijayakumar 2016). This is generally compatible with the
“MCS-51” instruction set and pinout. Reprogramming of the program memory is allowed by the
on-chip FLASH in the system or by conversion of the non-volatile memory programmer.
Combination of the versatile 8-bit CPU with the FLASH that is present in the monolithic chip,
makes this microcontroller a very powerful microcomputer that is responsible for providing a
highly flexible and a solution which is very much cost effective to the embedded control
applications (Kithuka 2015).

17EMBEDDED SYSTEM DESIGN
Block diagram of ATMEL 89C51
The following features are provided by the ATMEL 89C51:
 FLASH of 4K bytes
 RAM of 128 bytes
 Input/output lines=32
 Two counter/timer of 16-bit

18EMBEDDED SYSTEM DESIGN
 A five vector two-level interrupt architecture
 Full duplex serial port
 Oscillator and clock circuitry on the chip
 Designed with a static logic so as to operate at a frequency of zero and to support two
power saving modes selected by the software.

19EMBEDDED SYSTEM DESIGN
Pin diagram of ATMEL89C51:
Instruction set of ATMEL 89C51:
Mnemonic Description Byte Oscillator
Period
ARITHMETIC INSTRUCTIONS

20EMBEDDED SYSTEM DESIGN
ADD A,Rn Add register to
Accumulator
1 12
ADD A,direct Add direct byte to Accumulator 2 12
ADD A,@Ri Add indirect RAM to
Accumulator
1 12
ADD A,#data Add immediate data to
Accumulator
2 12
ADDC A,Rn Add register to Accumulator with
Carry
1 12
ADDC A,direct Add direct byte to Accumulator
with Carry
2 12
ADDC A,@Ri Add indirect RAM to
Accumulator with Carry
1 12
ADDC A,#data Add immediate data to Acc with
Carry
2 12
SUBB A,Rn Subtract Register from Acc with
borrow
1 12
SUBB A,direct Subtract direct byte from Acc
with borrow
2 12
SUBB A,@Ri Subtract indirect RAM from
ACC with borrow
1 12
SUBB A,#data Subtract immediate data from
Acc with borrow
2 12
INC A Increment Accumulator 1 12
INC Rn Increment register 1 12
INC direct Increment direct byte 2 12
INC @Ri Increment direct RAM 1 12
DEC A Decrement Accumulator 1 12
DEC Rn Decrement Register 1 12
DEC direct Decrement direct byte 2 12

21EMBEDDED SYSTEM DESIGN
DEC @Ri Decrement indirect RAM 1 12
INC DPTR Increment Data Pointer 1 24
MUL AB Multiply A & B 1 48
DIV AB Divide A by B 1 48
DA A Decimal Adjust Accumulator 1 12
LOGICAL INSTRUCTIONS
ANL A,Rn AND Register to Accumulator 1 12
ANL A,direct AND direct byte to Accumulator 2 12
ANL A,@Ri AND indirect RAM to
Accumulator
1 12
ANL A,#data AND immediate data to
Accumulator
2 12
ANL direct,A AND Accumulator to direct byte 2 12
ANL direct,#data AND immediate data to direct
byte
3 24
ORL A,Rn OR register to Accumulator 1 12
ORL A,direct OR direct byte to Accumulator 2 12
ORL A,@Ri OR indirect RAM to
Accumulator
1 12
ORL A,#data OR immediate data to
Accumulator
2 12
ORL direct,A OR Accumulator to direct byte 2 12
ORL direct,#data OR immediate data to direct byte 3 24
XRL A,Rn Exclusive-OR register to
Accumulator
1 12

22EMBEDDED SYSTEM DESIGN
XRL A,direct Exclusive-OR direct byte to
Accumulator
2 12
XRL A,@Ri Exclusive-OR indirect RAM to
Accumulator
1 12
XRL A,#data Exclusive-OR immediate data to
Accumulator
2 12
XRL direct,A Exclusive-OR Accumulator to
direct byte
2 12
XRL direct,#data Exclusive-OR immediate data to
direct byte
3 24
CLR A Clear Accumulator 1 12
CPL A Complement Accumulator 1 12
RL A Rotate Accumulator Left 1 12
RLC A Rotate Accumulator Left through
the Carry
1 12
RR A Rotate Accumulator Right 1 12
RRC A Rotate Accumulator Right
through the Carry
1 12
SWAP A Swap nibbles within the
Accumulator
1 12
DATA TRANSFER INSTRUCTION SET
MOV A,Rn Move register to Accumulator 1 12
MOV A,direct Move direct byte to Accumulator 2 12
MOV A,@Ri Move indirect RAM to
Accumulator
1 12

23EMBEDDED SYSTEM DESIGN
MOV A,#data Move immediate data to
Accumulator
2 12
MOV Rn,A Move Accumulator to register 1 12
MOV Rn,direct Move direct byte to register 2 24
MOV Rn,#data Move immediate data to register 2 12
MOV direct,A Move Accumulator to direct byte 2 12
MOV direct,Rn Move register to direct byte 2 24
MOV direct,direct Move direct byte to direct 3 24
MOV direct,@Ri Move indirect RAM to direct
byte
2 24
MOV direct,#data Move immediate data to direct
byte
3 24
MOV @Ri,A Move Accumulator to indirect
RAM
1 12
MOV @Ri,direct Move direct byte to indirect
RAM
2 24
MOV @Ri,#data Move immediate data to indirect
RAM
2 12
MOV DPTR,#data16 Load Data Pointer with a 16-bit
constant
3 24
MOVC A,@A+DPTR Move Code byte relative to
DPTR to Acc
1 24
MOVC A,@A+PC Move Code byte relative to PC to
Acc
1 24
MOVX A,@Ri Move External RAM (8- bit
addr) to Acc
1 24

24EMBEDDED SYSTEM DESIGN
MOVX A,@DPTR Move Exernal RAM (16- bit
addr) to Acc
1 24
MOVX @Ri,A Move Acc to External RAM (8-
bit addr)
1 24
MOVX @DPTR,A Move Acc to External RAM (16-
bit addr)
1 24
PUSH direct Push direct byte onto stack 2 24
POP direct Pop direct byte from stack 2 24
XCH A,Rn Exchange register with
Accumulator
1 12
XCH A,direct Exchange direct byte with
Accumulator
2 12
XCH A,@Ri Exchange indirect RAM with
Accumulator
1 12
XCHD A,@Ri Exchange low-order Digit
indirect RAM with Acc
1 12
BOOLEAN VARIABLE MANIPULATION INSTRUCTION SET
CLR C Clear Carry 1 12
CLR bit Clear direct bit 2 12
SETB C Set Carry 1 12
SETB bit Set direct bit 2 12
CPL C Complement Carry 1 12
CPL bit Complement direct bit 2 12
ANL C,bit AND direct bit to CARRY 2 24
ANL C,/bit AND complement of direct bit to
Carry
2 24

25EMBEDDED SYSTEM DESIGN
ORL C,bit OR direct bit to Carry 2 24
ORL C,/bit OR complement of direct bit to
Carry
2 24
MOV C,bit Move direct bit to Carry 2 12
MOV bit,C Move Carry to direct bit 2 24
JC rel Jump if Carry is set 2 24
JNC rel Jump if Carry not set 2 24
JB bit,rel Jump if direct Bit is set 3 24
JNB bit,rel Jump if direct Bit is Not Set 3 24
JBC bit,rel Jump if direct Bit is set & clear
bit
3 24
ACALL addr11 Absolute Subroutine Call 2 24
LCALL addr16 Long Subroutine Call 3 24
RET Return from Subroutine 1 24
RETI Return from interrupt 1 24
AJMP addr11 Absolute Jump 2 24
LJMP addr16 Long Jump 3 24
SJMP rel Short Jump (relative addr) 2 24
JMP @A+DPTR Jump indirect relative to the
DPTR
1 24
JZ rel Jump if Accumulator is Zero 2 24
JNZ rel Jump if Accumulator is Not Zero 2 24
CJNE A,direct,rel Compare direct byte to Acc and
Jump if Not Equal
3 24

26EMBEDDED SYSTEM DESIGN
CJNE A,#data,rel Compare immediate to Acc and
Jump if Not Equal
3 24
CJNE Rn,#data,rel Compare immediate to register
and Jump if Not Equal
3 24
CJNE @Ri,#data,rel Compare immediate to indirect
and Jump if Not Equal
3 24
DJNZ Rn,rel Decrement register and
Jump if Not Zero
2 24
DJNZ direct,rel Decrement direct byte and Jump
if Not Zero
3 24
NOP No Operation 1 12
Summary of comparison:
Components
ATMEL 89C51 PIC16F84A ATmega328P
Bus width 8-bit for standard core 8/16/32-bit 8/32-bit
Speed 12 Clock/instruction
cycle
4 Clock/instruction
cycle
1 clock/ instruction
cycle
Memory ROM, SRAM, FLASH SRAM, FLASH Flash, SRAM,
EEPROM
ISA CLSC Some feature of RISC RISC
Memory Architecture Von Neumann
architecture
Harvard architecture Modified
Power Consumption Average Low Low

27EMBEDDED SYSTEM DESIGN
Families 8051 variants PIC16,PIC17, PIC18,
PIC24, PIC32
Tiny, Atmega, Xmega,
special purpose AVR
Community Vast Very Good Very Good
Manufacturer NXP, Atmel, Silicon
Labs, Dallas, Cyprus,
Infineon, etc.
Microchip Average Atmel
Cost (as
compared to features
provide)
Very Low Average Average
Other Feature Known for its Standard Cheap Cheap, effective
Conclusion:
The rising market of electronics has greatly influenced the way in which the
microcontrollers are being used. In today’s world the microcontrollers are very much cheap and
can be obtained very simply. They are generally used instead of the easy logic circuits. In the
upcoming future the world is going to be fully automated where the use of robots and electronic
devices will increase. Most of this electronic gadgets would run only with the help of numerous
microcontrollers and would produce the results without any type of errors. Due to the fact that
the fresh microcontrollers are “IN SYSTEM PROGRAMMABLE” so they have the capability of