EEE/CSE 120 Design Project
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Added on 2019-09-19
EEE/CSE 120 Design Project
Added on 2019-09-19
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Hardware Lab 4: EEE/CSE 120 Design ProjectFall 2016Background: The Scoring in ScrewballThere is a game called Screwball. Every time a ball is put in play, either player 1 scores a pointor player 2 scores a point. A winner is declared when one player is ahead by 2 points. Startingwith a score of 0:0 for P1 vs. P2, a game might progress as follows:0:11:12:13:1 (P1 Wins!)The Application: The Win AnnouncerYour task is to develop a synchronous sequential machine that uses information about whichplayer scores a point at each stage of a game to indicate BOTH when a player wins and whichplayer wins. Your design should include one reset input to initialize your WIN ANNOUNCER(this may be a synchronous or asynchronous input as you desire). The outputs from your designshould indicate BOTH when a win has occurred and which player is the winner. All information to complete this design may not be specified. Write down and report anyassumptions that you make in your design.Be sure to use debounced “logic switches” for driving the clock input to the flip-flops.DeliverablesYou are to design two CONCEPTUALLY different finite-state synchronous machines. Adesign which differs only by the type of flip flop used (e.g., J-K vs. D)or number of states is notconsidered conceptually different.First, you will need to implement both designs using Logisimand demonstrate to the CSE/EEE 120 simulation TA’s in GWC 185 that both designs work correctly by the software duedate (See Table 1 below). You may demo this by either 1) opening your file using the computer reserved by the TA on dutyor 2) asking the TA to test your circuit on your laptop. You will need to bring with you aprintout of your report template into which you’ve cut/pasted your Logisim circuits. Itmakes most sense to complete the lab template and print it before you go and demonstrate thedesigns to the TA. You must have your design simulation working before asking the TA totest it because you will be given only one chance to prove that it works.You must also beable to defend your design; the TA’s will be asking questions to make sure that your design isyour own original work. Upon completion of your simulation demonstration, the TA’s will signand apply a grade to your report template. You also need to include these simulations into yourlab report template. Second, you will need to implement ONE design using the TTL parts you used in earlier labwork and demonstrate to only a CSE/EEE 120 hardware TA that your circuit workscorrectly. You must complete this demo by the due date (See Table 1 below). After reviewingthe simulation TA’s signature on your Logisim schematic printout, the hardware TA’s will testyour design and stamp the design pages of your completed report template. You must be able toexplain why your circuit responds the way it does to a given input data stream. You must haveyour report template completed and bring it with you to your in-lab hardwaredemonstration. Your completed report template will be collected by the hardware TA at the
conclusion of your demonstration.You must use the design project template for your report.Lab project make-ups will be allowed ONLY with written permission from your instructor.You may discuss this project with each other; however, you must provide an individual report.In addition:•You must go to the GWC 185 individually to demonstrate your simulationof both designs AND (Write up the Lab Report BEFORE you come to the hardware lab).•You must go to the hardware lab individually to build one circuit in orderto have your individual report count.Grading PolicyThe grade will be allocated as follows:30% Design Simulation With Logisim•15% for the design of the first circuit and demonstration.•15% for the design of the second circuit and demonstration.•70%BuildOneDesignintheH
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