Princeton's IAS Computer: Structure, Operation, and Instruction Cycles

This presentation provides a comprehensive overview of the IAS (Institute for Advanced Study) computer, developed by John Von Neumann. It details the computer's characteristics, including its physical dimensions, word length, and the significance of its design. The presentation delves into the IAS structure, explaining the roles of key components such as the Memory Buffer Register (MBR), Memory Address Register (MAR), Instruction Register (IR), Instruction Buffer Register (IBR), Program Counter (PC), Accumulator (AC), and Multiplier Quotient (MQ). It further elucidates the Central Processing Unit (CPU) and its function in data processing. The presentation also covers the instruction cycles, differentiating between the fetch and execute cycles, and outlines various instruction types, including data transfer, unconditional and conditional branches, arithmetic operations, and address modification. Additionally, it discusses different scales of integration (SSI, MSI, LSI, VLSI, and VVLSI) and touches upon floating-point representation. The presentation concludes by highlighting the key features of the IAS computer and its impact on computer design.

IAS Computers

Characteristics of IAS machine
 Developer: It was developed by John Von Neumann in between 1945 to 1951 at the
Princeton University
 Goal: To make the computer designs more efficient and practical
 Measurement: 299.72 cm X 320.04 cm X 83.83 cm
 Words: 1000
 Word Length: 40 bit (1 sign bit and other 39 bits represent the number)
10 39
Sign Bit Number

IAS Structure

IAS Structure (Contd.)
MBR (Memory Buffer Register): comprises a word
that is to sent, received or stored to the memory.
MAR (Memory Address Register): states the
memory address of the word that is to be stored or
read.
IR (Instruction Register): The 8 bit opcode is
executed

IAS Structure (Contd.)
IBR (Instruction Buffer Register): It is used for holding the word in the memory
PC (Program Counter): Comprises of the next available memory address
AC (Accumulator) and MQ (Multiplier Quotient): Used to store operands
CPU (Central Processing Unit): Handles all the operations of the computer and also used
for data processing operations (Hwang and Jotwani 2016).

computers

Instruction Cycles
FETCH CYCLE EXECUTE CYCLE
Opcode of the next instruct
is stored in the IR while
address is stored in the MAR
(Lang 2015).
The instruction is gathered
from IBR
It is obtained in the
memory by storing the word
in the MBR and then to IBR,
IR and again MAR
The handling circuitry
interprets provided opcode
to it.
Then it operates the
instruction by providing the
control signals
The data or the instruction
is moved to the ALU
(Arithmetic Logical Unit)

Various Instructions of IAS computer
Data Transfer: This instruction move all the data
either among the memory and the ALU or between
two ALU.
Unconditiional Breach: The handling unit operates
the instructions in order from the memory.
Conditional breach: Branch are prepared
depending upon the condition.

Various Instructions of IAS computer
(contd.)
Arithmetic: Comprises of various arithmetic operation that are operated by the
Arithmetic Logic Unit.
Address Modify: It helps a user by providing them permission to use a memory
address

Various scale of Integration
SSI (Small Scale Integration): It comprises of less
than hundred elements (10 gates)
MSI (Medium Scale Integration): It comprises of less
than 500 elements or greater than 100 gates.
LSI (Large Scale Integration): In this case the number
of elements is in the range of 500 to 300000 and thus
comprises of more than 100 gates

Various scale of Integration
(contd.)
VLSI (Very Large Scale of Integration): VLSI comprises
of greater than 300000 elements in each chip
VVLSI (Very Very Large Scale of Integration): It
contains greater than 1500000 elements in each chip.

Floating Points
Representation:
Addition
Subtraction
Biased exponent significand
Sign of
significand 8 bits 23 bits