Integrated Circuit Design Project: 4-bit ALU (6310ENG/7513ENG)

This project report details the design and simulation of a 4-bit Arithmetic Logic Unit (ALU) using Electric CAD. The project, completed as part of an Integrated Circuit Design course (6310ENG/7513ENG) at Griffith University, focuses on minimizing layout area, delay, and power consumption using CMOS technology. The report covers the project's introduction, design principles, theories, and implementation details, including the use of various logic gates and modules to perform arithmetic and logical operations such as addition, subtraction, multiplication, and bitwise operations. The ALU design incorporates considerations for operating speed, power consumption, and footprint optimization. The project includes detailed schematics and layouts, with results and analysis of the ALU's functionality and performance. The report also covers the use of MOSIS technology and discusses the extra outputs responsible for carry and overflow during addition, absolute, and subtraction operations. The design includes three selectors (S0, S1, and S2) to select operations and extra outputs like Cout and V.

6310ENG/7513ENG Design Project

Chapter 1
Introduction
The technology has advanced these days creating a possibility in scaling down the
electronics that has a lot of applications. The application of different technology has made engineers
and designers to become more and more thoughtful about portability. The selling point being that
the power requirements at that level impacts the circuit even more, that is, when power is
dissipated there’ll be an increase in heat, and decrease in stability, this in turn brings the
performance down. This is the main problem of design and many proposals have been made over
the years of how to overcome issues of these nature. Adiabatic logic has been resorted to as a way
of reducing this problem in CMOS, so that power dissipation is reduced without compromising with
the ability to drive and immunity, and numerous adiabatic Logics are fronted each time and many
over the years already but the primary principles is still the same (Sharma, et al., 2012).
This project involves the designing, in detail, of an implementable Electric Very Large-
Scale Integration (VLSI), of a 4 – bit Arithmetic Logic Unit (ALU) and simulating it using Electric CAD.
An ALU is the fundamental component of a central Processing unit (CPU), which performs operation
that involves arithmetic like addition, subtraction, division and multiplication of binary numbers and
logical operations like AND, OR, NOT among and other Boolean algebraic functions. Addition of the
binary functions, binary adder circuit is the basic unit of ALU, among others, that does operations of
arithmetic functions. The binary adder has different configurations based on how it carries out the
operations. It faces constraints like the area of the chip, power consumption and speed. Apart from
the requirement of the design, ALU has a specific functionality which it achieves. This design project
has different logic gates that will aid in the design of ALU. Table 1 shows the different logic
operations that are included in the design of ALU. The 4-bits inputs used in the ALU are A and B
named from A0 to A3 and B0 to B3 respectively. The apart from the multiplication operation, which
needs 8-bits outputs, the other outputs used are R0 to R3 for all the other operations.
Table 1: The designed ALU operations
S2 S1 S0 Arithmetic Operation Output C V
0 0 0 Addition of A and B A+B 0/1 0/1
0 0 1 Subtraction of B from A A-B 0/1 0/1
0 1 0 Left shift B by one Bit Left B 0 0
0 1 1 Negative A 0 - A 0 0
1 0 0 Negative B 0-B 0 0
1 0 1 Absolute A-B |A-B| 0/1 0/1
1 1 0 Multiplication of A and B AxB 0 0
1 1 1 Minimum selector Min A, B 0 0
The remaining bit of it, that is R4 to R7, are involved in the addition of the extra output during
multiplication. After designing the ALU, there will be three selectors, i.e. S0, S1, and S2, that selects
operations. To add to it, there are outputs in the subtraction, multiplying the two’s compliment, and
computing negative A and B. The designed ALU will also have some extra outputs, they are cout
(which is the value of C) and V. These are responsible for carry and deal with excess during addition,
absolute and subtraction. The table also clearly shows that C and V values results in 0, except adder,
absolute and subtraction, then the value of the three operation, adder subtraction and absolute,
contain an over flow and a cout depending on the result, which would give 1 or 0. This technology

used here is CMOS and MOSIS technology. Resulting from the table, the final product is what is
shown in figure 1.
Figure 1: The Icon of an ALU
Chapter 2
The Theories and Basic design
There are two essential principles required in the design of an ALU, operating speed, power
consumption and footprint. This design like any other shall incorporate those principles as well and
they start from planning of the design so that a correct design is undertaken. The principles
considered in achieving a good design can be borrowed from software manual (Static Free Software,
2019). As mentioned earlier, there are four functions of select inputs, S0 to S3 and control unit mode
(M), ALU is able to perform the 16 possible arithmetic and logic operations when there’s an active
HIGH or LOW operands. When the control mode M is high, all the carries internally becomes
inhibited and the gadget performs logic operations on each bits. On the other hand, when M reads
LOW, this triggers the carries to be enabled and arithmetic operations are performed by ALU on 4-bit
words which are two.
Before executing the design, it is important to consider the operating speed and the power
consumption, also the foot print so that a correct circuit design is carried through. Footprint for
instance is done by reducing the transistors number by carefully designing the individual modules.
By doing this, the most basic logic gates can be used wherever possible, like the NOR and NAND
gates. But in places where complicated logic circuits shall be needed, these basic logic gates shall be
combined to have a more effective footprint use area. This can end up reducing the power
consumption and have the speed increased.