Intelligent Memory: Overcoming Processor-Memory Performance Gap

Running head: TOPIC SUMMARY: INTELLIGENT MEMORY
Topic Summary: Intelligent Memory
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1TOPIC SUMMARY: INTELLIGENT MEMORY
Summary of Intelligent Memory
Definition: The growth of technology has helped in developing the Microprocessor and
Dynamic Random Access Memory or DRAM technology for the organization
(Prizedwriting.ucdavis.edu, 2017). The implementation of the operations was helpful in carrying
the system of the development of the speed and capacity of the memory devices. The
Microprocessor was helpful in increasing the speed of the operations of the memory devices and
the DRAM has made it possible for increasing the capacity of the memory devices. The
Processor-Memory Performance Gap is an issue that results due to the difference in the function
of the technologies of Microprocessor and Dynamic Random Access Memory or DRAM and it
impacts in causing the issue of bottleneck in the system. The problem arises when the memory
system competes with the devices for getting data to the CPU and it results in increasing the
overall time duration. The problem results in making the computing power of the computer
operation cycles idle and non-useable. The Intelligent Memory is a specially designed
architecture of the memory structure that can help in overcoming the issue of Processor-Memory
Performance Gap (Selman, Aburas & Selman, 2014). It helps in maximizing the data transfer
and CPU functions with the help of smarter technologies.
Architectural Description: There are four models of Intelligent Memory that has been
used prominently for development and improvement. They are Active Pages, Computational
RAM (CRAM), Parallel Processing RAM (PPRAM), and Intelligent RAM (IRAM) (Ahn, Yoo,
Mutlu & Choi, 2015). The development of the denser chips with the help of DRAM technology
has made the development for Intelligent Memory more effective. It has helped in exhausting
only 10 sq mm instead of 50 sq mm for developing 64 MB of the RAM. The Active Pages model

2TOPIC SUMMARY: INTELLIGENT MEMORY
has divided the memory of the DRAM in equally sized pages that has assign the logic block in
each of the page. The logic block has only the die area for development of a simple circuitry.
Hence the more complex operations for example Float Point Arithmetic has to be done in the
CPU. However, a complete query consists of both simple and complex functions. The complex
functions are operated in the CPU and the simple functions are operated in the memory. The task
breakdown and task partitioning is a function deployed in Active Pages. The CRAM has very
similar function to the Active pages and it also considers the placement of the processing blocks
in DRAM chips. The CRAM model has enormous internal bandwidth with 1.1 terabytes per
second (Selman, Aburas & Selman, 2014). The connection pins are placed on the memory chips
that would help in yielding the 270 megabytes per second and it makes the external bandwidth of
the 4000 less than the internal bandwidth.
The issue is that these little capacitors store so little charge that the interior wiring will
retain the signs previously they escape the chip. To take care of this issue, DRAM architects put
"sense speakers" on inner wires to support the yield signals. The processor has two 1-bit
registers, X and Y, and a self-assertive capacity Arithmetic Logic Unit (ALU)
(Prizedwriting.ucdavis.edu, 2017). This ALU acknowledges two information sources and places
the 1-bit yield onto the outcome transport. One of the two ALU input ports (call it 'A' for
simplicity of reference) has three bits, originating from enroll X, Y, and the sense intensifier. The
other info port, 'B', contains a 8-bit guideline from the worldwide transport. Basically, the ALU
is a multiplexor with 'A' being the 3-bit selector that controls which one of the 8-bits from 'B'
gets set onto the outcome transport. A PPRAM framework is comprised of different PPRAM
hubs and these hubs have 3 parts: a rationale hinder, a memory piece, and a correspondence
square. The rationale square can be anything from a broadly useful processor to an I/O controller