Interconnecting of Design Subsystem Assignment

Added on - 13 Apr 2020

  • 14

    Pages

  • 357

    Words

  • 99

    Views

  • 0

    Downloads

Trusted by +2 million users,
1000+ happy students everyday
Showing pages 1 to 4 of 14 pages
FPGA SOURCEFILES
(1)counterInterconnecting of design subsystemProcedureUsing debugStep-1the using vivado tools, select the Flow navigator, under the project manager, andselect the IP catalog commandStep-2this IP catalog window is search field, search for the VIO (virtual input/output) IPcore. After that selected the VIO core, in the details window, under represent the main IP
catalog window, all necessary information will find the about select IP core window.Step-3Double-click on the VIO(Virtual input/output) IP core and Vivaado IDE will createand select skeleton source for your VIO core.
Step-4 using this VIO (input/output) window enter in vio, core name (vio core) in thecomponent name field,Step-5 go to general option tab and select the input probe count to be 1 and output probecount also to be 1,because the input probe for pwm out signal and one outut probe for sw()signalStep-6 this PROBE_IN ports (0, 0) tab leave the probe width of the PROBE_INO probe portto be 1, because our pwm out signal.
desklib-logo
You’re reading a preview
Preview Documents

To View Complete Document

Click the button to download
Subscribe to our plans

Download This Document