Physics of Semiconductor Devices | Report

Physics of Semiconductor Devices 1
PHYSICS OF SEMICONDUCTOR DEVICES
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Physics of Semiconductor Devices 2
FABRICATION AND ELECTRICAL MEASURMENTS OF MIS BASED MEMORY DEVICES.
Maximum Marks = 100 (25 % towards module total marks)
Lab report -2

1. Abstract
This paper research on memory devices which are based
on Metal Insulator Semiconductors for example flash
memory. The use of memory devices are so significant
in storage of data and get accessed when there is a need.
In most cases memory devices are categorized into RAM
and ROM. This paper is more focused on the fabrication
of these memories which are electrically based devices.
2. INTRODUCTION
MEMORY devices are playing an increasingly
important role in microelectronics technology and
considered as the technology drivers, whereas electronic
memories cover about 20% of semiconductors market.
Memory devices can be divided into different categories
as shown in Fig. 1.
Figure 1: Different types of solid-state memories.
Basically, these memory devices are divided into two
types, i.e. volatile memories and non-volatile memories.
The speed of write-erase operations in volatile memories
such as SRAM and DRAM are very high, while these
memories will lose data when the supply voltage is
removed. In contrast, non-volatile memories have a very
low write-erase speed with the need for high voltage and
a longer retention time, usually more than 10 years.
These different types of memories have different
functions or in other words, fill a particular function in a
particular system. For example, SRAM memories are
used by microprocessors of computers as off-chip or on-
chip cache to store copies of the most frequently used
main memory locations, to reduce the average time to
access memory. SRAM memories are expensive and
have a very high write-erase speed compared to the other
type of volatile memories such as DRAM memories.
DRAM memories are used as the main memory in
computers and provide a random-access storage that is
relatively large and cheap as compared to SRAM and
relatively fast as compared to non-volatile memories.
Magnetic disks are considered as a storage device and
have the advantage of providing high storage capacity at
extremely low cost, but with a poor energy consumption
and a low access speed capabilities compared to other
memory devices. For example, nine million instructions
can be executed by a 3-GHz microprocessor while
waiting for the data from the magnetic disk. A broad
range of computing systems was designed to conceal the
disagreeable performance of magnetic disks. Because of
critical computing applications are becoming data-
centric, a high performance, high density and low cost
NVM technology, which access time falls between of
that of HDD and DRAM will increase the overall system
performance [1]. Flash memories technology promises
to provide Hard Disks with costs lower than Magnetic
disk cost. In Flash memories, the elapsed time between
data storage and the first invalid readout of the data is
the retention time. Each non-volatile storage technology
employs a particular storage mechanism and properties
related to that mechanism [1]. Its implementation format
will verify the retention features of the device. For Flash,
the storage mechanism is to represent data by quantities
of charge held on a floating gate. Each technology can
be expected to have some natural processes where the
data representation changes with time. Flash has some
intrinsic charge decay characteristics that define the
ultimate retention potential of the approach. At the
present time, a typical retention specification is 10 years.
3. Aim and Objective:
The aim of the experiment is to fabricate and electrically
characterise Metal-Insular-Semiconductor structures
containing silicon nano-structures fabricated from a
selected catalyst (tin) as a charge-storing element.
A b
Figure 2:Schematic diagram of MIS structure (a) a
reference device without containing any nano-
structures (b) a memory device containing nano-
structure as a floating gate
4. Fabrication of MIS structures:
All the fabrication steps will be carried out using various
equipment available in the EMTERC research group. A
p-type silicon substrate, having a thin native oxide (1-2
nm) will be provided. Cleaning of the silicon wafer is
performed using a standard organic solvents cleaning
procedure. The bottom contact is performed by
evaporating Aluminium and annealing in N2 gas at
500oC to establish an ohmic contact. The polished side
of Si wafer is coated with Sn, of thickness 3 nm
(approximately), by thermal evaporation. This is then
Insulator
Semiconductor
Ohmic contact
Control gate
Control gate
Insulator
Floating gate
semiconductor
Ohmic contact