Desklib - Online Library for Study Material with Solved Assignments, Essays, Dissertations

This document discusses the basic concepts of PN junction, diodes, bipolar junction transistors, and field-effect transistors. It also includes a design for a BJT-based amplifier using emitter stabilization DC bias method. The document covers various topics such as depletion zones, forward and reverse bias, voltage drops, and current flows. It also includes AC and DC models for transistors and hybrid-pi models for FETs. The document is relevant for students and instructors studying analogue and digital electronics.

Student
Instructor
Analogue and digital electronics
Date

2
Section 1: PN Junction
1.1 Basic Semiconductor Concept
1.1.1
I. Boron
II. Aluminum
They all have 3 valence electrons (Laube).
1.1.2
I. Phosphorus
II. Antimony
They have 5 valence electrons (Laube).
1.2 PN junction (diode) basic
1.2.1
Depletion zone of P-N junction is formed by intimate contact between p-type and
n-type semiconductors such that crystal structure remains continuous at the boundary.
The junction has a transition of a very short thickness, 1micro, from p-type material to n-
type material. The p-type which forms the anode has acceptor atoms while n-type which
forms the cathode, has donor atoms. Majority carriers in p-type are holes while minority
charge carriers are electrons. Majority charge carriers through diffusion process, move

3
from high concentration region to a region of low concentration hence forming
concentration gradient. For n-type majority carriers are electrons while minority carriers
are holes. Positive and negative ions are immobile charge carriers. At the junction, holes
in p-type recombine with electrons in the n-type leaving only acceptor and donor
immobile ions in the depletion layer. When enough electrons have accumulated the p-
region, more electrons diffusing from n-region are repelled. A similar case for holes from
p-region diffusing to the n-region are repelled. The action leads to a state of equilibrium
with fixed immobile negative and positive ions at near the junction with no charge
carriers. Barrier voltage across the depletion layer barricades the movement of charge
carriers across the depletion layer (Nave).
1.2.2
The junction is forward biased by applying a positive voltage at the p-type and negative
voltage at the n-type, mobility majority charge carriers results to more flow of current as
a result of reduced depletion layer (Nave).
When reverse voltage is applied, a constant small reverse current flow due to mobility
of minority charge carriers as a result of increased depletion layer.
1.2.3
The ebullient circuits and corresponding Voltage verses Current curves of a diode when
considering it as 1) ideal diode, 2) practical diode with voltage drop, 3) practical diode
with voltage drop and resistance

4
1) Ideal diode
2) Practical diode with voltage drop

5
3) Practical diode with voltage drop and resistor
1.3 PN Junction (Diode) Applications
1.3.1
If the diode has a forward voltage drop 𝑉𝐷 = 0.6𝑉 and 𝑅𝐷 = 10Ω, use the practical
diode DC model to calculate current flowing in the circuit in Fig 1.3.1. (3 Marks) 5 V
100Fig 1.3.1
I D = ( 5−V D ) V
RΩ 100
I D = ( 5−0.6 ) V
100 Ω
I D =0.044 A

6
1.3.2
It is a biased combination diode clipping circuit.
The clipped waveform
1.3.3
This is a full wave bridge rectifier. It consists of four diodes and during each cycle, only two
diodes conduct.
Full wave rectifier

7
During the positive cycle, D2 is forward-biased while D1 is negative-biased. Current flows
through D2 to the load and return current flows back through diode D3.
During the negative cycle, D4 is forward-biased while D3 is negative-biased. Current flows
through D4 to the load and return current flows back through diodeD1.
The biasing voltage for diodes is 0.7V and hence there is no conduction during the period 0-
0.7V. The output waveform is shown below.
D2
D3
D4
D1

8
Output wave of the full wave rectifier
1.4
Block diagram of AC/DC power supply
The first stage is the transformer stage that steps down voltage to a lower level that can
be fed to the rectification stage. The rectification stage comprises of a bridge rectifier circuit that
converts AC voltage to DC voltage. This is the block that uses diodes for full wave rectification.
The diodes are forward-biased in pairs for each cycle resulting in a DC output for each cycle.
The next stage is the smoothing circuit that comprises a shunt capacitor which eliminates ripples
in the dc wave from the rectification stage. The final stage is the regulation stage that outputs a
constant DC voltage.
Transformer Rectification Smoothing
circuit Regulation
AC
Input
DC
Output

9
Section 2: Bipolar Junction Transistor
2.1 BJT Bias Circuit
Need to stabilize Q point are as explained below
I. To select operating point ( I c ,V CE) i.e operating regions of BJT either in saturation
mode, cut-off mode or active mode.
II. To maintain selected operating point
III. To avoid thermal runaway
Examples of BJT d.c bias circuit that can stabilize Q point.
The voltage divider bias can be used to set a Q point independent of β which varies with current
and temperature hence impossible to get stable Q point if it is used and it is shown above.

10
This is the collector feedback scheme which maintains constant Q. This is due to the fact that an
increase in collector current causes a decrease in base drive by increasing the collector voltage
drop. The reduction in base drive will reduce the collector current thereby maintaining Q point.
2.2 BJT DC Model
2.2.1
From the DC analysis, the DC load line equation is:
V CE= V CC - I C( RC + RE)
Making I C the subject:
I C = - V CE
( RC + RE ) + V CC
( RC +RE )
This equation is analogous to the equation of a straight line y=mx + c
The y-intercept is calculated by equating V CE to zero:

11
I C = V CC
( RC + RE ) = 20
( 4 K +5 K) = 2.22 mA
The x-intercept is calculated by equating I C to zero:
V CE= V CC = 20V
Q point is marked using parameters I CQ and V CEQon the DC load line.

12
2.2.2
From AC analysis, the following parameters are calculated:
Base voltage
V B = RB 2
( RB 1+RB 2 ) * V CC
V B= 10 k
(20 K +10 K ) * 20 = 6.7V
Emitter voltage
V E= V B- V BE= 6.7-0.7=6V
Emitter current
I E = V E
RE
= 6/5k = 1.2mA
But I E = I C = I CQ
Hence
V C = V CC - I C RC = 20 – (1.2m*4k) = 15.2V
V CE= V CEQ= V C- V E= 15.2-6 = 9.2V
Using the above parameters to calculate for the ac load line end points:
vCE= V CEQ + I C RC = 9.2 + 4.8 = 14V

13
iC sat = I CQ+ V CEQ
RC
= 1.2m + (9.2/4k) = 3.5mA
Saturation and cut off point on the AC load line differ from those on the DC load line because
the AC collector and emitter resistance are lower than their respective DC resistance.
2.3 BJT AC Model/Hybrid-pi Model

14
Finding the parameter for h-pi module.
Short-circuiting D.C sources, coupling and by-pass capacitors
Finding RTH of the circuit
RTH = Rb 1 Rb 2
Rb 1+Rb 2

15
RTH =20 X 10
20+10 =6.67 kΩ
hie =ro =1 kΩ,
Finding equivalent load resistance
R 'L=RL /¿ RC /¿ ro
R'
L=0.52 K
Finding the conductance
gm = I c
V T
=2,22 mA
25 mV =0.088 A
V (Ic from the previous calculation)
Finding r π
r π = β
gm
= 150
0.088 =1.689 K (hfe=β=150)

16
Finding voltage gain
Av=V out
V ¿
=−gm
R 'i
( R 'i + Ri ) R 'L
Where R 'i= RTH r π
RTH + rπ
=1.348 KΩ
Substituting the value to get Av
Av=−0.088 1.348
( 1.348+1 ) 0.52 K =26
Section 3: Field Effect Transistor
3.1 Semiconductor basic of FET
Field effect transistors are voltage control current devices because they utilize an electric
field to control their conductivity. In the case of JFETs, the depletion region grows as the reverse
bias across the PN junction increases thereby increasing resistance of the channel. The gate
voltage regulates current flowing through the JFET. Similar to the latter, MOSFETS control the
current flowing through the drain and source with the gate voltage. The only difference is that for
MOSFETs the gate is insulated from the conducting material. This property of isolation in FETs
make them desirable in inputs of measuring instruments due to a high input impedance, less
noise and low power consumption.
3.2 FET DC Model
3.2.1

17
Saturation mode is achieved when the gate-source voltage, V GS is zero.
The drain current, I D is expressed as:
I D = I DSS [1− V GS
V P ]2
I D = I DSS (V GS = 0)
The source voltage is expressed as:
V S = V G - V GS , but V GS = 0 hence
V S = V G
The source voltage V S is calculated as:
V S = V G = V DD
4 = 10
4 = 2.5V
Using a voltage divider bias to express gate voltage as a function of V DD:
V G= ( R2
R1 + R2 ) V DD
Making R2 the subject:
R2 = V G
V DD
( R1 +R2 )
R2 = 2.5
10 ( 100 k )
R2 = 25kΩ

18
Since R1 + R2= 100 kΩ
R1= 100 kΩ - 25kΩ = 75kΩ
Solving for RD:
RD= V DD −V DS
I D
RD= 10−5
5 mA = 1kΩ
R1 = 75kΩ
R2 = 25kΩ
RD = 1kΩ
3.2.2
JFET is basically a variable controlled voltage resistor whose linear region is achieved by
controlling drain to source resistance r by using bias voltage V GS so as to operate in the ohmic
region, which is linear part of the I-V curve with constant transconductance.

19
III.3 FET AC Model/Hybrid-pi Model
AC equivalent circuit of FET
Let R1 /¿ R2=¿R 1
R=75 K X 25 K
75 K +25 K
¿ 18.75 kΩ
Voltage gain , Av= V out
V ¿
2
But V out =−gm vgs RD 3
And vgs=v¿ 4
Substituting equation 4 in 3
vout=−gm RD v¿

20
Av=−gm ( 1 KΩ )
Boost Section
Task:
Design a BJT based amplifier which includes the following features:
1. Using NPN BJT
2. Using Emitter Stabilisation DC bias method
3. Have one AC input signal
4. Using necessary capacitors to separate the AC and DC signals
The amplifier circuit designed on multisim is shown below:

21
The NPN transistor used was BC547A. The emitter resistance chosen to stabilize the amplifier’s
bias voltage was a 390-ohm resistor. The input AC Signal was 30mV Vrms at a frequency of the
recommended 60Hz. The collector resistance was chosen as 2.2k-ohm. The voltage divider
network was comprised of resistors of 18k-ohm and 3.3k-ohm. V DD was chosen as 12V.
The following transistor characteristics were derived:

22
Plot of I B vs V BE
Plot of I Cvs V CE
The simulated results of the input and output were were:

23
Input and output waves
The input signal was fed to channel A which was set to display on the upper part of the
oscilloscope screen. The output was fed to channel B and both signals set to the same amplitude
to show the amplification of the input signal.
The voltage gain as calculated from the results of the simulated circuit is:
AV = V o
V i
= 161.345 mV
−24.974 mV = -6.46
From circuit the voltage gain can also be calculated as:
AV = - RL
RE
= - 2.2 K
390 = -5.64
The value obtained from the simulation does not vary widely with the theoretical value and the
difference can be reduced further with another set of resistor values for the amplifier circuit.

24
Works cited

25
Laube, Philipp. “Fundamentals: Doping: N- And P-Semiconductors.” Semiconductor
Technology from A To Z, Halbleiter.Org,2014.
<https://www.halbleiter.org/en/fundamentals/doping/>
Nave, R. “Depletion region.” PN Junction, Hyperphysics, 2017. <http://hyperphysics.phy-
astr.gsu.edu/hbase/Solids/pnjun.html/>