Research Methods for Engineers Assignment 2022

RESEARCH METHODS FOR ENGINEERS
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Title: MANAGING OVERHEADS IN PARTIALLY RECONFIGURABLE FPGAs
Introduction
Field programmable gate arrays, FPGAs, have developed from being chips that are used in the
implementation of glue-logic to arenas for implementation of advanced mixed systems of
hardware and software-on-chips. With their sizes and capabilities being on the increase, FPGAs
have established applications in an avalanche of domains in which their programmability
provides exclusive benefits compared to fixed applications [1]. An outstanding advantage of
reconfigurable computer systems revolves around their capability of reconfiguring hardware to
delivering high performance or reducing consumption of energy. Hence, reconfiguration
computing systems might attain the needs imposed by embedded systems. An integral part of
partial reconfiguration revolves around reconfiguration overhead that is often inclusive of
runtime reconfiguration time as well as the static storage space for reconfiguration data. The two
costs are directly linked with the physical partial reconfiguration file size. In as much as previous
researches have illustrated optimized accelerators, limited focus has been put on leverage of
runtime partial configuration property in reducing the consumption of energy by the chip.
Literature Review
Dynamic power and static power are the two major power consumption sources within a
reconfigurable computing system. Consumption of static power takes place due to leakage
current within transistor even as dynamic power consumption takes place when the transistor is
switching.
Shang et al. (2002) analyzed consumption of dynamic power of Xilinx Virtex-II FPGAs and
their findings demonstrated the role of dissipation of dynamic power for logic, routing as well as
clocking resources to be 16 per cent, 60 per cent and 14 per cent in that order [3]. Tuan et al.
(2003) explored leakage of power for a 90 nm FPGA with the aid of elaborate device-level
simulations and established that statistic consumption of static power was associated with inputs
to configuration memory, junction temperature as well as utilization of chip resource [5]. Li et al.
(2003) came up with power simulation for studying power efficiency in FPGAs within 0.10 um
technology where they established power leakage within deep sub-micron FPGAs may be to the
tune of 50% of cumulative power, emphasizing on the need of techniques for reducing static
power [4].