TTL and CMOS Logic Families

Logic gates are grouped not just by their respective logical functions but as well by their logical families. In any given implementations of any digital system, a comprehension of the physical capabilities and limitations of a logical element as determined using the logic family are quite important to proper operation. This article discusses TTL and CMOS logic families, their characteristics, differences, and applications. It covers the power dissipation, propagation delays, voltage levels, noise immunity, fan-out, and fan-in of each logic family.

TTL AND CMOS LOGIC FAMILIES
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TTL and CMOS logic families
Logic gates are grouped not just by their respective logical functions but as well by their logical
families. In any given implementations of any digital system, a comprehension of the physical
capabilities and limitations of a logical element as determined using the logic family are quite
important to proper operation (Hairapetian, 2018).
The logic family defines the general physical realization of a logical element, for example, TTL,
ECL or even CMOS logic families. TTL is an abbreviation for Transistor-Transistor Logic while
CMOS stands for Complementary Metal Oxide Semiconductor even as ECL stands for Emitter-
Coupled Logic. Within each of the logic, the family is a single or multiple more logic series
which have distinctive features relative to the other series within the same family of logic
(Bindal, 2017).
CMOS logic TTL logic
Dissipates low power. The power dissipated depends
on the voltage of the power supply, output load,
frequency, and input rise time
The power dissipation is often 10mW per gate
Propagation delays are short. The propagation delays
are often about 25nS to 50nS depending on the supply
of power
The propagation delays are often 10nS when
driving a 15 pF/400 ohm load
The levels of voltage range from 0 to VDD in which
VDD refers to the supply voltage. A low level is found
anywhere between 0 and 1/3 of VDD whereas a high
level is found between 2/3 VDD and VDD
The levels of voltage range from 0 to Vcc in which
Vcc is normally 4.75V-5.25V. A voltage range of
0V-0.8V generates logic level 0; voltage range 2V-
Vcc generates logic level 1
There is control in the rise and fall times. The rise and
fall times are often ramps as opposed to step functions
and are often 20-40% longer than propagation delays
((Bindal, 2017))
There is no control in the rise and fall times
Noise immunity of the family approaches 50% to 45%
of full logic swing
Poor noise immunity less than CMOS
Logic signal levels will be equal to the amount of
power supplied as the input impedance is very high
Logic signal levels will not be equal to the amount
of power supplied as the input impedance is very
average
Fan-out is 50 Fan-out is 10
Fan-in is more than 10 Fan-in is about 12-14

Simple to construct; higher packing density Low packing density
CMOS compared to TTL
CMOS components are often more expensive in comparison with TTL parts. Nonetheless,
CMOS technology is often less costly on a system level owing to CMOS chips which are smaller
and need minimal regulation (Sisodia, Kumar and Punetha, 2015).
The susceptibility to damage of CMOS components due to electronic discharge is higher as
compared to the components of TTL
CMOS circuits don’t draw as much power in comparison with TTL circuits while not in use.
Nonetheless, the consumption of power by CMOS increases with an increase in the speed of
clocks as compared to TTL. During of lower current requires less distribution of power supply
hence resulting in a simple and cheaper design (Damti, Watkins and Stanley, 2016).
Owing to the longer rise and fall times, digital signals transmission tends to be simpler and less
costly with CMOS chips.
Figure 1: Propagation Delay Times
Explanation of technical terms

Fan-in refers to the maximum inputs number to a gate. It is influenced by the number of pins
that can be put on IC packages as well as their standardization.
Fan-out refers to the number of standard loads which the output of a gate can drive without
causing impairment to its normal functioning. A standard load is the amount of current needed to
drive an input of another gate in the same family of logic (Damti, Watkins and Stanley, 2016).
Noise immunity defines a digital circuit’s ability to avert changes in the logic levels on signal
lines when noise results in changes in the levels of voltage.

References
Hairapetian, A., Avago Technologies General IP (Singapore) Pte Ltd, 2018. Current-controlled
CMOS logic family. U.S. Patent Application 15/793,595
Bindal, A., 2017. TTL Logic and CMOS-TTL Interface. In Electronics for Embedded
Systems (pp. 89-122). Springer, Cham
Sisodia, A.K., Kumar, P. and Punetha, D., 2015, May. Design, analysis, and optimization to
mount different logic families in a single IC. In 2015 Second International Conference on
Advances in Computing and Communication Engineering (pp. 388-391). IEEE
Damti, S.M., Watkins, S.E. and Stanley, R.J., 2016, April. Comparison of binary and multi-level
logic electronics for embedded systems. In Industrial and Commercial Applications of Smart
Structures Technologies 2016 (Vol. 9801, p. 98010L). International Society for Optics and
Photonics