Designing a Virtual Memory Manager

Designing a Virtual memory manager
Approach used in designing of a virtual memory.
This is a technique that involves providing storage resources’ layer of abstraction that are available
on a given machine. The operating systems uses both the hardware and the software that are used to
map memory addresses called virtual to physical addresses. The main storage contains segments of
continuous addresses spaces. Address translation is also referred to as memory management.
Memory management is the process of converting the virtual addresses in the main memory to the
physical addresses.
The advantages of virtual memory include freeing the application from the problem of sharing the
same addresses space or having to share the same memory. The concept of paging is applicable to
solve the issue of memory allocation (Gorman, 2014).
Handling page fault
A page fault comes about when a program attempts accessing the data that is in the address space
that is not found or has no existence in the system RAM.
When the page fault comes about, the operating system checks the addresses space that caused the
fault to occur. If the virtual address that cause the fault is found and is valid, the system for any free
page frame, if none of the pages is found to be free, the algorithm of page replacement is run to
remove the pages.
(i) Check data in the address space
(ii) if page fault occurs
(iii) check the addresses causing the
(iv) fault if addresses found
(v) check if the addresses are
(vi) valid if addresses valid
(vii) run the page replacement algorithm
(viii) removes the pages
Address Translation
This involves translating logical addresses to physical addresses, TLB and the page table are used
during the mapping of the logical addresses to physical addresses. The TLB must in sync and
checked in order to access the physical addresses from the TLB. If a TLB-hit occurs, the addresses

Designing a Virtual memory manager
are no longer checked from the TLB but instead the frame is obtained from the TLB. In the latter if
a miss takes place the TLB must be accessed to check the frame (Rogers & Swanberg, 2015).
Results and discussion.
The program reports:
- Page fault rate – this is the percentage of addresses that resulted in the page faults.
- TLB hit rate - this is the percentage of the addresses spaces that were in the TLB.