This document contains solutions for VLSI Techniques-ELEC 30007 –SPRING-2018 – CW1–QP. It includes calculation of resistance of polysilicon wire, design of half adder circuit using CMOS transistors, drawing stick diagram of half-adder circuit and determining optimum operation of the circuit.
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VLSI Techniques-ELEC 30007 –SPRING-2018 – CW1–QP 1.Calculate the resistance of the polysilicon wire as shown in following figure. The polysilicon wire is fabricated using 1μm technology. Given RS=6 ohm/square. Figure1: Polysilicon wire Solution: R=Rs∗l w Rs=6w=3λ=1μMl=49λ=16.333μM Therefore: ELEC 30007 (QP)Page1of7 Assignment - SPRING 2018 Module:VLSI Techniques (ELEC 30007)ID NUMBER Level: 3Max. Marks: 100
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VLSI Techniques-ELEC 30007 –SPRING-2018 – CW1–QP b.Draw the stick diagram of Half-adder circuit. Solution: Figure3:Stick diagram of Half-adder circuit c.Appropriate device sizing can result in equal and symmetrical drive current which leads to a sustainable design. In order to obtain optimum operation of the circuit determine the(W L)p,eq and(W L)n,eq for the half adder circuit. Assume that(W L)p =30 for all PMOS transistors and (W L)n =15for all NMOS transistors. Solution: Total PMOS transistors=8 Total NMOS transistors=8 Series: (W L)EQ =1 (W L)1 +(W L)2 +…. ELEC 30007 (QP)Page4of7
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VLSI Techniques-ELEC 30007 –SPRING-2018 – CW1–QP Parallel: (W L)EQ =(W L)1 +(W L)2 +… (W L)p,eq =30∗3+1 30∗3+1 2∗30=90.0278 (W L)n,eq =2 15∗2+15∗4=60.067 ELEC 30007 (QP)Page5of7
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VLSI Techniques-ELEC 30007 –SPRING-2018 – CW1–QP Sachdev, M., Pineda De Gyvez, J., & Sachdev, M. (2007).Defect-oriented testing for nano-metric CMOS VLSI circuits. Dordrecht, Springer. Available from: http://public.eblib.com/choice/publicfullrecord.aspx?p=371648. [Accessed 29thApril 2018]. ELEC 30007 (QP)Page7of7