Finite State Machine (FSM) for Process Control System

This document discusses the design and implementation of a Finite State Machine (FSM) in a process control system. It explains the input, present state, next state, and flip-flop input of the FSM. The document also includes a state transition table and the use of Karnaugh maps to simplify the logical expressions of the D flip-flops.

ELECTRICAL ENGINEERING
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Table of Contents
Question 1:.................................................................................................................................................2
Question 2:.................................................................................................................................................3
Question 3:.................................................................................................................................................7
Question 4:.................................................................................................................................................8
Question 5:...............................................................................................................................................10
VHDL Code:........................................................................................................................................11
Block Diagram of Shift Register:.......................................................................................................12
Test Bench Program:..........................................................................................................................14
Question 6:...............................................................................................................................................14
VHDL code:.........................................................................................................................................16
References................................................................................................................................................18
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Question 1:
Simplify the circuit given in Figure 1. Briefly explain your solution and draw the resulting
simplified circuit using only OR gates.
Figure 1: Circuit diagram
Hint: simplify the logic gates with constant-value inputs.
Truth Table of the above diagram XNOR Truth Table
A A` B B
`
OUT
0 1 0 1 0
1 0 1 0 1
OR gate Truth Table AND gate Truth Table
When A`=1 and B`=1
The output of first level is
Output of OR gate = 1 and output of AND gate1 = 1 (refer Truth table of AND gate and OR
gate)
Now the above two outputs are given as two inputs to the AND gate2.
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In1 In2 OUT
0 0 1
0 1 0
1 0 0
1 1 1
In1 In2 OUT
0 0 0
0 1 1
1 0 1
1 1 0
In1 In2 OUT
0 0 0
0 1 0
1 0 0
1 1 1

The Output of AND gate2 = 1 (for the inputs (1,1)) (refer Truth table of AND gate)
One of the input is 1 and the other input is 0 (given) for XNOR gate.
Hence the output obtained finally from the XNOR gate is OUT = 0
When A`=0 and B`=0
The output of first level is
Output of OR gate = 1 and output of AND gate1 = 0 (refer Truth table of AND gate and OR
gate)
Now the above two outputs are given as two inputs to the AND gate2.
The Output of AND gate2 = 0 (for the inputs (1,0)) (refer Truth table of AND gate)
One of the input is 0 and the other input is 0 (given) for XNOR gate.
Hence the output obtained finally from the XNOR gate is OUT = 1
Question 2:
(i) Consider a logic function with the standard minterm canonical form:
f(A,B,C,D)= ∑
m
(0,2,8,9,10,12)
(ii) Write the function in the standard maxterm canonical form.
Solution:
The standard maxterm for the given function is given as
f ( A , B ,C , D ) =∑m (0,2,8,9,10,12)
(iii) Implement the function f using one multiplexer having appropriate number of
inputs.
Solution:
Implementation Table: f ( A , B ,C , D )=∑m (0,2,8,9,10,12)
I0 I1 I2 I3 I4 I5 I6 I7
4
A B C D Standard Minterms (Product Terms)
0 0 0 0 m0= A . B .C . D
0 0 1 0 m2= A . B . C . D
1 0 0 0 m8= A . B .C . D
1 0 0 1 m9= A . B .C . D
1 0 1 0 m10= A . B . C . D
1 1 0 0 m12= A . B . C . D
A B C D Standard Maxterms (Sum Terms)
0 0 0 0 M 0= A+B+C +D
0 0 1 0 M 2= A+B+C +D
1 0 0 0 M 8=+B+C + D
1 0 0 1 M 9= A+ B+C + D
1 0 1 0 M 10= A+B+C+ D
1 1 0 0 M 12=A + B+C+D

A’
1 3 4 5 6 7
A
11 13 14 15
1 A 1 0 A 0 0 0
The output of 8:1 Mux are given as,
I0 = I2 = 1 (logic 1)
I1 = I4 = A
I3 = I5 = I6 = I7 = 0 (logic 0)
8:1 MUX :
(iv)Implement the function f using one decoder having appropriate number of inputs, and a
logic gate.
Solution: f ( A , B ,C , D ) =∑m (0,2,8,9,10,12)
5
0
8 9 10
2
12
I0
I1
I2
I3
8:1 MUX Y
I4
I5
I6
I7
S2 S1 S0
Logic 1
A
Logic 0
F
B
C
D
I0
I1
I2
I3
A 4 – to – 16 I4
B Decoder I5
CI6
DI7
I8
I9
I10
I11
I12
I13
I14I15

(v) Write the logical expression of the function f.
The logical expression of the function f ( A , B ,C , D ) =∑m (0,2,8,9,10,12) is given as
f = A . B . C . D+ A . B . C . D+ A . B . C . D+A . B . C . D+ A . B .C . D+ A . B .C . D
(vi)Using Boolean algebra rules, give the most simplified logical expression of the function
f. Show the details of your work.
Solution:
Simplified logical expression of the function f ( A , B ,C , D ) =∑m (0,2,8,9,10,12) is
given as
f = A . B . C . D+ A . B . C . D+ A . B . C . D+A . B . C . D+ A . B .C . D+ A . B .C . D
f = ( A . B . C . D+ A . B . C . D ) + ( A . B . C . D+ A . B . C . D ) + A . B .C . D+ A . B .C . D
f = A . B . D ( C .+C . ) + A . B .C ( D+D )+ A . B .C . D+ A . B .C . D [ Boolean rule: C .+C=1]
f = A . B . D+ A . B . C+ A . B .C . D+ A . B .C . D
(vii) Using Karnaugh map, give the most simplified logical expression of the function
f. Show the details of your work.
00 01 11 10
00 1 1
01
11 1
10 1 1 1
Grouping 1
¿ A . B . C . D+ A . B . C . D+ A . B . C . D+ A . B .C . D= A . B . D ( C +C ) + A . B . D ( C +C ) =A . B . D+ A . B . D=B . D
Grouping 2¿ A . B . C . D+ A . B . C . D= A . C . D ( B+B ) = A .C . D
Grouping 3¿ A . B . C . D+ A . B . C . D= A . B . C ( D+D ) =A . B . C
f =B . D+ A . C . D+ A . B . C
6
AB
CD
Gropuping1
Gropuping2 Gropuping3

(viii)Using the most simplified logical expression of the function f, draw the resulting circuit
of the function using only NAND gates (even to generate the inverse of an input).
f =B . D+ A . C . D+ A . B . C
Logic Diagram:
(ix)Write a VHDL entity to model the function f.
library ieee;
use ieee.std_logic_1164.all;
entity digm is
port (A,B,C,D: in std_logic;
f:out std_logic);
end digm;
architecture digmarch of digm is
component not1
port(B:in std_logic; Bbar: out std_logic);
end component;
component not2
port(C:in std_logic; Cbar: out std_logic);
end component;
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B’
D’
C’
D’
A
C’
B’
A

component not3
port(D:in std_logic; Dbar: out std_logic);
end component;
component and1
port(Bbar,Dbar:in std_logic; x1: out std_logic);
end component;
component and2
port(A,Cbar,Dbar:in std_logic; x2: out std_logic);
end component;
component and3
port(A,Cbar,Dbar:in std_logic; x3: out std_logic);
end component;
component or1
port(x1,x2,x3:in std_logic; y: out std_logic);
end component;
begin
F1:or1 port map(x1,x2,x3,y);
end digmarch;
Question 3:
A sequence detector has a single binary input and a single binary output. The output of the
detector should turn immediately to logic 1 when the pattern 0110 is received in the input stream
with overlap patterns. Here is an example of input-output sequence:
Input : 111011011011
Output : 000000100100
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a/1
b/0
d/0
c/0
1
0
00
11
0

 Give a Finite State Machine (FSM) transition diagram of the above system.
Solution:
The above diagram gives the transition diagram of the system.
In order to obtain the repeated sequence ‘0110’, the system is designed with states.
Consider there are 4 states in the system. a,b,c and d with two inputs 0 and 1.
The system starts with the initial state ‘a’.
When the input is 0, the system enters into the next state ‘b’ with output 0. And when
the input is 1, the system remains in the same state with output 0.
Now the next state ‘b’ is considered.
When the input of state ‘b’ is 0, the system remains in the same state. And when the input
is 1, the system enters into the next state.
Next the system enters the state ‘c’.
When the input to the system is 1, the system enters the next state’s’. And when the input
is 0, the sequence is not in order. Therefore, again the system enters into the state ‘a’.
Finally the system enters into the state ‘d’.
When the input is 0, the sequence gets completed as ‘0110’. Therefore, the system
produces the output 1 and again it resets to repeat the sequence.
Question 4:
Figure 4 gives the diagram of a Finite State Machine (FSM) used in a process control system.
The FSM has one input, one output and three states.
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Figure 4: FSM diagram
(i) Name the model of the above FSM. Explain your answer.
The model describes the state machine in the automation process (Rani, Fatima, Kalra &
Sinha, 2017).
The system works in a sequence. There are three states in the FSM. Each state has its
own criteria. If it is satisfied, the state proceeds with the next state. Else it maintain in the
same state, till it reaches the condition.
(ii) Design an efficient digital circuit of this FSM using D-type flip-flops. In your answer,
you should include the following:
Input Present state Next State Flip – Flop Input
X A B A+1 B+1 DA DB
0 0 0 0 0 0 0
0 0 1 1 0 1 0
0 1 0 0 0 0 0
0 1 1 1 0 1 0
1 0 0 0 1 0 1
1 0 1 0 1 0 1
1 1 0 1 1 1 1
1 1 1 0 1 0 1
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(a) State transition table
Present state
Next state
x=0 x=1
S0 S0 S2
S1 S1 S2
S2 S1 S2
(b) Karnaugh maps to get simplified logical expressions of the D flip-flops inputs and the
FSM output.
Let us consider the present states as : A and B and the next state as A+1 and B+1 with
input x.
DA DB
00 01 11 10
0 0 1 1 0
1 0 0 0 1
DB=x A + xBA
DA=x
(iii) Verify in Logisim software the correctness of your designed digital circuit.
Discuss the results of your simulation. (The Logisim design circuit and simulation log
file should be both submitted.)
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AB
x
AB
00 01 11 10
0 0 0 0 0
1 1 1 1 1
x

Question 5:
Figure 5.2 gives the internal structure of the 8x32 Register file shown in Figure 5.1.
The structure has an internal array of eight 32-bit registers where data is stored. It allows two
simultaneous combinational reads from the array of registers. The inputs “Rs” and “Rt” select
the two array registers whose values are set on “Rs_output” and “Rt_output”, respectively. The
structure allows one synchronous write operation on the registers array when the enable signal
“Regwrite” is set to one; the value of “Rd” selects the element of the registers array to update
with the value of “Rd_Data”.
Figure 5.1: Register file interface
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Figure 5.2: Structure of the register file.
The ports “En” in the figure refer to the enable pins of the 32-bit registers.
 Using VHDL structural modelling (design by hierarchy), write and test the VHDL entity
to model the system of Figure 5.1. To get full credit, the testing should be
comprehensive covering all the possible cases of the architecture functionality.
VHDL Code:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity stregfile is
Port ( ta : in std_logic_vector(4 downto 0);
tb : in std_logic_vector(4 downto 0);
tw : in std_logic_vector(4 downto 0);
wr : in std_logic;
clk : in std_logic;
bW:in std_logic_vector(31 downto 0);
bA : out std_logic_vector(31 downto 0);
bB : out std_logic_vector(31 downto 0));
end stregfile;
architecture sregstr of stregfile is
type reg_file is array (31 downto 0) of std_logic_vector(31 downto 0);
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signal regarray:reg_file(0 to
31):=(x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"0000
0000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"000
00000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00
000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"0
0000000",x"00000000",x"00000000",x"00000000",x"00000000");
begin
process(ta,tb,tw,wr,clk,bW)
variable addr_a,addr_b,addr_w:integer;
begin
addr_a:=CONV_INTEGER(Ra);
addr_b:=CONV_INTEGER(Rb);
addr_w:=CONV_INTEGER(Rw);
bA<=regarray(addr_a);
bB<=regarray(addr_b);
if (clk'event and clk='1') then
if (Regwr='1') then
regarray(addr_w)<=busW;
end if;
end process;
end sregstr;
Test Bench Program:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Tb_ stregfile is
end Tb_ stregfile;
architecture RTL of Tb_ stregfile is
component stregfile
ta : in std_logic_vector(4 downto 0);
tb : in std_logic_vector(4 downto 0);
tw : in std_logic_vector(4 downto 0);
wr : in std_logic;
clk : in std_logic;
bW:in std_logic_vector(31 downto 0);
bA : out std_logic_vector(31 downto 0);
bB : out std_logic_vector(31 downto 0));
end component;
signal :w_ta : integer;
signal :w_tb : integer;
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signal:w_tw : integer
signal:w_wr : integer;
signal:w_clk : integer=0;
signal:w_bW: integer
signal:w_bA : integer
signal:w_bB : integer
begin
out: stregfile
port map(
ta => w_ta ;
tb => w_tb;
tw => w_tw;
wr => w_wr;
clk => w_clk;
bW => w_bW;
bA => w_bA ;
bB => w_bB ;
SIMULI : process
begin
bA=0;
bB=0;
wait for 20 ns;
w_clk=2;
wait for 10 ns;
wait;
end process;
end Test;
Block Diagram of Shift Register:
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n – bit Shift Register Serial
Out
Serial In
Parallel
In Parallel
Out

The shift register is a sequential logic circuit which is used for the storage and the transfer of
binary data. The sequential device loads the data present with its inputs. It then shifts it to its
output once every clock cycle(LIU, MIAO, ZENG & LIU, 2011). Hence the name is given as
shift register. In general for any n-bit shift register, there are three control inputs namely, preset,
clear and clock. The shift register works on the concept of latch. Either a logic “0” or a “1”,
connected together in a serial type arrangement so that the output from one data latch becomes
the input of the next latch and so on. Data bits are fed in or out of a shift register serially. The
arrangement of transfer of bit is one after the other from either the left or the right direction, or
all together at the same time in a parallel configuration (Sharma & Rana, 2013). The number of
bits to be stored is determined by the number of individual data latches required to make up a
single Shift Register. The device is the most common of 8-bits (one byte) wide constructed from
eight individual data latches. Shift Registers are mainly used for storage of data and for the
movement of data. Therefore, shift registers are used in commonly used inside calculators or
computers to store data such as two binary numbers before they are added together. It also used
to convert the data from either a serial to parallel or parallel to serial format. The individual data
latches that make up a single shift register are all driven by a common clock ( Clk ) signal
making them synchronous devices (Lee, 2014).
Shift registers are classified into four different modes with the basic movement of data through a
shift register being:
 Serial-in to Parallel-out (SIPO) - The register loads the data serially. One bit at a time,
with the stored data that is being available at the output in parallel fashion.
 Serial-in to Serial-out (SISO) - The data is shifted serially in. The register moves one bit
at a time in either a left or right direction under clock control.
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Preset
Clock
Clear

 Parallel-in to Serial-out (PISO) - The data is loaded in parallel form into the register
simultaneously and is shifted out of the register serially one bit at a time under clock
control.
 Parallel-in to Parallel-out (PIPO) - The parallel data is loaded simultaneously into the
register, and transferred together to their respective outputs by the same clock pulse.
Question 6:
Modulation is a process of mixing the input signal information with a carrier to produce a new
signal suited to the characteristics of a transmission channel. Figure 6.1 gives the interface of our
Transmitter system, where a 2-bit input symbol will be converted into a specific modulation
waveform as follows:
 Symbol 00, Wav0= [0,32,64,32,0,-32,-64,-32]
 Symbol 01, Wav1= [0,64,127,64,0,-64,-128,-64]
 Symbol 10, Wav2=[ 0,-32,-64,-32,0,32,64,32]
 Symbol 11 , Wav3=[ 0,-64,-128,-64,0,64,127,64]
Figure 6.1: Transmitter interface
In Idle state, the outputs of the Transmitter:
 “Start” is at level 1
 “Busy” is at level 0
 “Data” value is 0
The Symbol generator (SG) generates a 2-bit symbol at random times. The presence of the data
is flagged by a pulse on the “Load” output. The “Load” pulse is asynchronous to the Transmitter
“Clk” signal; it occurs at random times; its width is considerably smaller than the Transmitter
Clk cycle.
Once the SG generates a symbol, the Transmitter,
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(i) Latches the symbol at the rising edge of the “Load” pulse.
(ii) If the “Busy” output is already 1, no new action is taken.
(iii) If “Busy” is 0, the following sequence happens:
(a) At the next “Clk” rising edge, the output “Start” is set to 0 for one “Clk”period.
(b) At the next “Clk” rising edge, the “Busy” signal is set to 1 for 8 “Clk”cycles.
(c) From the next “Clk” rising edge, the Transmitter starts to send on its “Data”
output the 8-long sequence of the waveform corresponding to the latched symbol,
one sample at every CLK cycle.
Figure 6.2 gives the timing diagram of Figure 6.1 signal waveforms.
Figure 6.2: Timing diagram of Figure 6.1 structure
 Model and test in VHDL the system of Figure 6.1 as exactly described above. To get full
credit, the testing should be comprehensive covering all the possible cases of the
architecture functionality.
VHDL code:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity mapper_ask is
port (
i_clk : in std_logic;
i_rstb : in std_logic;
i_meta_sym : in std_logic_vector(1 downto 0);
o_mapper : out std_logic_vector(7 downto 0));
end mapper_ask;
architecture rtl of mapper_ask is
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type t_mapper_table is array(0 to 3) of integer range 0 to 255;
constant mapper_table : t_mapper_table := (
63,
127,
191,
255);
signal r_meta_sym : integer range 0 to 3; -- used as mapper_table pointer
begin
p_mapper_ask : process(i_clk,i_rstb)
begin
if(i_rstb='0') then
r_meta_sym <= 0;
o_mapper <= (others=>'0');
elsif(rising_edge(i_clk)) then
r_meta_sym <= to_integer(unsigned(i_meta_sym));
o_mapper <= std_logic_vector(to_unsigned(mapper_table(r_meta_sym),8));
end if;
end process p_mapper_ask;
end rtl;
Test Bench
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Tb_mapper_ask is
end Tb_mapper_ask;
architecture RTL of Tb_mapper_ask is
19

component mapper_ask
i_clk : in std_logic;
i_rstb : in std_logic;
i_meta_sym : in std_logic_vector(1 downto 0);
o_mapper : out std_logic_vector(7 downto 0));
end component;
signal w_i_clk : integer:= 0;
signal w_i_rstb : integer:=1;
signal w_i_meta_sym : integer;
signal w_o_mapper: integer;
begin
out: mapper_ask
port map(
i_clk => w_i_clk,
i_rstb => w_i_rstb,
i_meta_sym => w_i_meta_sym,
o_mapper => w_o_mapper);
SIMULI : process
begin
o_mapper = 0
wait for 30 ns;
w_i_clk <= 2;
w_i_rstb <= 5;
w_i_meta_sym <=10;
wait for 20 ns;
wait;
end process;
end Test;
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References
Lee, M. (2014). An Artificial Intelligence Evaluation on FSM-Based Game NPC. Journal Of
Korea Game Society, 14(5), 127-136. doi: 10.7583/jkgs.2014.14.5.127
LIU, P., MIAO, H., ZENG, H., & LIU, Y. (2011). FSM-Based Testing: Theory, Method and
Evaluation. Chinese Journal Of Computers, 34(6), 965-984. doi: 10.3724/sp.j.1016.2011.00965
21

Rani, P., Fatima, S., Kalra, Y., & Sinha, R. (2017). Realization of all optical logic gates using
universal NAND gates on photonic crystal platform. Superlattices And Microstructures, 109,
619-625. doi: 10.1016/j.spmi.2017.05.046
Sharma, H., & Rana, C. (2013). Designing of 8-bit Synchronous FIFO Memory using Register
File. International Journal Of Computer Applications, 63(16), 23-26. doi: 10.5120/10551-5736
22