Finite State Machine (FSM) for Process Control System

ELECTRICAL ENGINEERING
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Table of Contents
Question 1:.................................................................................................................................................2
Question 2:.................................................................................................................................................3
Question 3:.................................................................................................................................................7
Question 4:.................................................................................................................................................8
Question 5:...............................................................................................................................................10
VHDL Code:........................................................................................................................................11
Block Diagram of Shift Register:.......................................................................................................12
Test Bench Program:..........................................................................................................................14
Question 6:...............................................................................................................................................14
VHDL code:.........................................................................................................................................16
References................................................................................................................................................18
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Question 1:
Simplify the circuit given in Figure 1. Briefly explain your solution and draw the resulting
simplified circuit using only OR gates.
Figure 1: Circuit diagram
Hint: simplify the logic gates with constant-value inputs.
Truth Table of the above diagram XNOR Truth Table
A A` B B
`
OUT
0 1 0 1 0
1 0 1 0 1
OR gate Truth Table AND gate Truth Table
When A`=1 and B`=1
The output of first level is
Output of OR gate = 1 and output of AND gate1 = 1 (refer Truth table of AND gate and OR
gate)
Now the above two outputs are given as two inputs to the AND gate2.
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In1 In2 OUT
0 0 1
0 1 0
1 0 0
1 1 1
In1 In2 OUT
0 0 0
0 1 1
1 0 1
1 1 0
In1 In2 OUT
0 0 0
0 1 0
1 0 0
1 1 1

The Output of AND gate2 = 1 (for the inputs (1,1)) (refer Truth table of AND gate)
One of the input is 1 and the other input is 0 (given) for XNOR gate.
Hence the output obtained finally from the XNOR gate is OUT = 0
When A`=0 and B`=0
The output of first level is
Output of OR gate = 1 and output of AND gate1 = 0 (refer Truth table of AND gate and OR
gate)
Now the above two outputs are given as two inputs to the AND gate2.
The Output of AND gate2 = 0 (for the inputs (1,0)) (refer Truth table of AND gate)
One of the input is 0 and the other input is 0 (given) for XNOR gate.
Hence the output obtained finally from the XNOR gate is OUT = 1
Question 2:
(i) Consider a logic function with the standard minterm canonical form:
f(A,B,C,D)= ∑
m
(0,2,8,9,10,12)
(ii) Write the function in the standard maxterm canonical form.
Solution:
The standard maxterm for the given function is given as
f ( A , B ,C , D ) =∑m (0,2,8,9,10,12)
(iii) Implement the function f using one multiplexer having appropriate number of
inputs.
Solution:
Implementation Table: f ( A , B ,C , D )=∑m (0,2,8,9,10,12)
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A B C D Standard Minterms (Product Terms)
0 0 0 0 m0= A . B .C . D
0 0 1 0 m2= A . B . C . D
1 0 0 0 m8= A . B .C . D
1 0 0 1 m9= A . B .C . D
1 0 1 0 m10= A . B . C . D
1 1 0 0 m12= A . B . C . D
A B C D Standard Maxterms (Sum Terms)
0 0 0 0 M 0= A+ B+C + D
0 0 1 0 M 2= A+ B+C + D
1 0 0 0 M 8=+ B+C + D
1 0 0 1 M 9= A+ B+C + D
1 0 1 0 M 10= A+ B+C + D
1 1 0 0 M 12=A + B+C+ D

I0 I1 I2 I3 I4 I5 I6 I7
A’
1 3 4 5 6 7
A
11 13 14 15
1 A 1 0 A 0 0 0
The output of 8:1 Mux are given as,
I0 = I2 = 1 (logic 1)
I1 = I4 = A
I3 = I5 = I6 = I7 = 0 (logic 0)
8:1 MUX :
(iv)Implement the function f using one decoder having appropriate number of inputs, and a
logic gate.
Solution: f ( A , B ,C , D ) =∑m (0,2,8,9,10,12)
5
0
8 9 10
2
12
D
C
B
F
Logic 0
A
Logic 1 I0
I1
I2
I3
8:1 MUX Y
I4
I5
I6
I7
S2 S1 S0
I0
I1
I2
I3
A 4 – to – 16 I4
B Decoder I5
C I6
D I7
I8
I9
I10
I11
I12
I13
I14

(v) Write the logical expression of the function f.
The logical expression of the function f ( A , B ,C , D ) =∑m (0,2,8,9,10,12) is given as
f = A . B . C . D+ A . B . C . D+ A . B . C . D+ A . B . C . D+ A . B . C . D+ A . B . C . D
(vi)Using Boolean algebra rules, give the most simplified logical expression of the function
f. Show the details of your work.
Solution:
Simplified logical expression of the function f ( A , B ,C , D ) =∑m (0,2,8,9,10,12) is
given as
f = A . B . C . D+ A . B . C . D+ A . B . C . D+ A . B . C . D+ A . B . C . D+ A . B . C . D
f = ( A . B . C . D+ A . B . C . D ) + ( A . B . C . D+ A . B . C . D ) + A . B . C . D+ A . B . C . D
f = A . B . D ( C .+C . )+ A . B .C ( D+ D ) + A . B . C . D+ A . B . C . D [ Boolean rule: C .+C=1]
f = A . B . D+ A . B . C+ A . B . C . D+ A . B .C . D
(vii) Using Karnaugh map, give the most simplified logical expression of the function
f. Show the details of your work.
00 01 11 10
00 1 1
01
11 1
10 1 1 1
Grouping 1
¿ A . B . C . D+ A . B . C . D+ A . B . C . D+ A . B . C . D= A . B . D ( C+ C ) + A . B . D ( C+C ) = A . B . D+ A . B . D=B . D
Grouping 2¿ A . B . C . D+ A . B . C . D= A . C . D ( B+ B )=A .C . D
Grouping 3¿ A . B . C . D+ A . B . C . D= A . B .C ( D+ D )= A . B . C
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AB
CD
Gropuping1
Gropuping2 Gropuping3