ITC544 Assignment 2 Solution: RAM Chips and Instruction Set

This assignment solution for ITC544 covers several key concepts in computer architecture. The solution begins with an analysis of RAM chips, calculating the number of rows, columns, and banks based on given parameters. It then delves into instruction set design, determining the number of bits required for opcodes based on the number of operations. Furthermore, the solution explores different addressing modes, calculating effective addresses for immediate, direct, indirect, and indexed addressing. Finally, the assignment demonstrates the implementation of code using different instruction formats: 2-address, 1-address, and 0-address machines, showcasing the versatility of instruction sets in performing operations. This solution provides a comprehensive understanding of computer organization and assembly language principles.

Assignment 2: MARIE & ISA
Subject Code (ITC544)
Name:
ID:

1.
a) For RAM chips:
Rows = (256 * 210 * 210)/ (210 * 210) = 256
Columns = 128/32 = 4
b) Per memory word 4 RAM chips because it equal to number of columns
c) 20 address bits because 1024K = 220
d) 256 banks as number of banks equals to number of rows.
e) 28 address bits because 256M = 228.
2.
a) For 240 operations,
180 ≤ 240 ≤ 256
27 ≤ 240 ≤ 28
Hence, 8bits are required for the opcode.
b) As, for one address instructions, register address bits are 0. Therefore, address part
–
48 = opcode + address
address = 40 bits
c) 248 – 1
3.
a) Immediate:
AC = AC + 1000
AC = 500 + 1000
= 1500
b) Direct:
AC = AC + [1000]
AC = 500 + 1400
= 1900
c) Indirect:
AC = AC + [[1000]]
AC = 500 + 1300
AC = 1800
d) Indexed:
AC = 500 + [1000 + R1]
AC = 500 + [1000 + 200]
AC = 500 + 1000
AC = 1500
Page 1 of 3

4.
2 – address machines
LOAD R1, B
ADD R1, C
LOAD R2, D
SUB R2, E
MULT R1, R2
STORE A, R1
1 – address machines
LOAD B
ADD C
STORE TMP
LOAD D
SUB E
MULT TMP
STORE A
0 – address instructions
PUSH B
PUSH C
ADD
PUSH D
PUSH E
SUB
MULT
STORE A
Page 2 of 3