CMOS Circuit Design: Aspect Ratio Calculation for a Two-Input NOR Gate

This assignment focuses on the design of a simple CMOS circuit, specifically a two-input NOR gate. The solution begins with the calculation of the aspect ratio (W/L) of the transistors, a critical step in CMOS design. The provided specifications include voltage, mobility, and feature size parameters. The solution details the determination of the ratio, transistor sizing for NMOS and PMOS transistors, and the calculation of threshold voltages (Vth). The design process involves determining the saturation region, applying equations to determine the drain current (ID), and ensuring that the calculated aspect ratios meet the design requirements. The layout of the circuit is also discussed, including design rules for contact openings, polysilicon, and active regions to prevent short circuits and ensure proper functionality. The assignment also includes citations of relevant research papers, offering additional context and supporting the design decisions.

CMOS DESIGN 1
CMOS design
Name of student
Institution
Date

CMOS DESIGN 2
CALCULATION OF W/L OF THE CIRCUIT
You are required to design a simple CMOS circuit consisting of a two- input NOR gate. You are
required to show the layout (plan view) of the circuit, after calculating the aspect ratio (W/L) of
the transistors.
Specification:
Vpp=4V, VI=0.3V, Co=5x104 Fm2, electron mobility 0.1 m2V-18:1 hole mobility 0.05 m²V-'s-
1, minimum feature size 0.2 m, maximum alignment error 0.1 um. The area of the circuit should
be a minimum.
SOLUTION Vpp=4V, VI=0.3V, Co=5x104 Fm2, electron mobility 0.1 m2V-18:1 hole mobility 0.05 m²V-'s-1,
 minimum feature size 0.2 m,
 maximum alignment error 0.1 um.
 The area of the circuit should be a
minimum
Step 1
Determination of the ration N
L
FROM THE FIGURES provided; r = μ . e
μ . h ………...(equation 1)
But μ . e = 0.1 and μ . h = 0.05
Thus we replace the figures back to the equation (1)
; r = 0.1
0.05
; r = 2 (number of input)

CMOS DESIGN 3
Thus, we begin with:
Nmos size of Wn= twice the length (Wn=2L).
L= 0.2μm thus;
Wn= 2 x L
= 2 x 0.2
= 0.4μm
Applying the valve in the equation
( ℘
L ) Pmos =λ N ( Wn
L )nmos
¿ ( ℘
0.2 ) Pmos
¿ 2 x 2 ( 0.4
0.2 )nmos
Wp = 1.6 μm
For the NOR gate in an inverter Vth is defined as Vin
BUT Vin = Vout = VA = VB = V DD
2 =3
2 =1.5V
ID3 = ID4 = ID1 + ID2
 Determining n-MOST M1 and M2:
VGSn = VA = Vth
VDSn = Vout = Vth = VGSn
Also,
VDSn > VGSn – VTn ,
Thus M1 and M2 are in saturation region.
IDn = IDn1 + IDn2 = μn Co w
Ln
= ( VGSn – VTn )2 = βn ( VGSn – VTn )
 Determining p-MOST M3 and M4:
M3:
VSGp = VDD - Vth ⟹VSGp = VDD - VD3 So, VSDp < VSGp - VTn

CMOS DESIGN 4
and the linear region.
ISDp = βp [ (Vth - VDD - VTp )VDSp3 - V DSp 3
2
2 ]
M4:
VSGp = VDD - VSD3 - Vth ⟹VSDp = VDD - VSD3 - Vth = VSGp
But,
VSDp > VSGp - VTn ,
Thus; M4 is in saturation region
ISDn = 1
2 βp( 2Vth + VSD3 - VTn )2
Applying the equation
∴ ID3 = ID4, so ISDn = ISDp ∵ 1
2 βp( 2Vth + VSD3 - VTn )2 = βp [ (Vth - VDD - VTp )VDSp3 -
V DSp 3
2
2 ]
VSDp3 = (√2−1 ¿ √ 2 I D
βp ⟹2
√ 2 ID
βp = VDD - Vth – VTp
Substituting ID
IDn = βn (VGSn - VTn)2
Vth =
2V Tn √ βp
βn (V DD+V Tp)
2+ √ βp
βn
Vtn = - Vtp ⟹ Vth = V DD
2 = 3
2 = 1.5V
(μn Co ) ( W n
Ln
¿ = 4 × (μp Co ) ( W p
Lp
¿
βn should be the same as βp
μn = 2 μp
W p
Lp
W n
Ln
=
1.6
0.2
0.4
0.2
=4 × 2=8

CMOS DESIGN 5
Hence
( W
L ¿ p=8( W
L )n
EXPLANATION
In the first instance of the calculation, we determined r, since it is needed for the purposes of
transition sizing in a two design, with two input NOR gate.
After determining the value of r (r=2), we consider that in the input NOR gate, the N-Mos are in
parallel, and P-Mos series. The threshold voltage will be effected by the aspect ratio
Hence, the value of VT is adjusted to BN/BP.
Scale
Scale:
Minimal Feature 0.5L 0.5L
L, smallest dimension 0.5 x 0.2μ 1 x 10−7
Wp 16 x 1 x 10−7 1.6 μ
Wn 4x 1 x 10−7 0.4 μ
L 2 x 1 x 10−7 0.2 μ
Explanation of design rules
used
The contact openings have been kept at least 2λ away from the poly-Si gates; this helps in
preventing a short circuit of the gate which might occur as a result of a short circuit of a metal
contact in the contact junction. In this way, the circuit will remain protected.
Minimal Feature 0.5L
L, smallest
dimension
1 x 10−7
Wp 1.6 μ
Wn 0.4μ
L 0.2μ

CMOS DESIGN 6
The polysilicon also have been used which is more than 2 λ past the active region, since, any case
slightest case of a misalignment might short circuit the gate.
Finally, the active regions have been surrounded by contacts which are at least 1 λ. This ensures
that any overlap which occurs within the surrounding does not result into a catastrophe from short
circuiting.
Coming down to the p-channel active region, it is surrounded by the n-well, by a margin of at least 3
λ, while the least spacing between the n-MOST junctions and the n well within the substrate is 5 λ.
The reason behind the spacing is that there is a great lateral diffusion of n-well, in addition to
preventing the circuit from being short circuited in the event that n-channel junction connected to the
n-well is short circuited
CMOS circuit
The MOS circuit has been built based on 4 transistors, with two being in series and the other
being in parallel. The output gate goes to logic gate 0, while two of the transistors are connected
between the gate and the ground, all being in parallel and in the n-channel. Where the output
goes to logic 1; there is a series connection of the transistors in p-channel region. Further, it can
be seen that the closest a p-channel and n-channel transistor can be connected is 8λ to inhibit
possibility of lateral diffusion in the n-channel. .

CMOS DESIGN 7
CIRCUIT LAYOUT

CMOS DESIGN 8
Work Cited
Martin, "Design of Two-Stage Class AB CMOS Buffers: A Systematic Approach", ETRI
Journal, vol. 33, no. 3, pp. 393-400, 2011. Available: 10.4218/etrij.11.0110.0465.
N. Geetha Rani, "Design of Near-Threshold CMOS Logic Gates", International Journal of VLSI
Design & Communication Systems, vol. 3, no. 2, pp. 193-201, 2012. Available:
10.5121/vlsic.2012.3216.
F. Silva, "Cmos integrated switching power converters: a structured design approach [book
news]", IEEE Industrial Electronics Magazine, vol. 6, no. 4, pp. 67-67, 2012. Available:
10.1109/mie.2012.2221359.
M. Aqeeli, "Design of a High Performance 5.0 GHz Low Phase Noise0.35μm CMOS Voltage
Controlled Oscillator", International Journal of Information and Electronics Engineering, 2013.
Available: 10.7763/ijiee.2013.v3.352.

CMOS DESIGN 9
S. Kousai, "Recent progress in CMOS RF circuit design", IEICE Electronics Express, vol. 11,
no. 2, pp. 20132011-20132011, 2014. Available: 10.1587/elex.11.20132011.
D. G and R. K.S, "A Low Power CMOS Analog Circuit Design for Acquiring Multichannel EEG
Signals", International Journal of VLSI Design & Communication Systems, vol. 6, no. 1, pp. 25-
37, 2015. Available: 10.5121/vlsic.2015.6103.
E. Rastegar Pashaki and M. Shalchian, "Design and simulation of an ultra-low power high
performance CMOS logic: DMTGDI", Integration, vol. 55, pp. 194-201, 2016. Available:
10.1016/j.vlsi.2016.06.004.
G. Nathiya and M. Balasubramani, "Design of Multiplier Using Low Power CMOS
Technology", SSRN Electronic Journal, 2017. Available: 10.2139/ssrn.2928962.