University Computer Architecture and Organization Homework Solution

This assignment solution addresses key concepts in computer architecture, including memory organization, instruction set design, and addressing modes. The solution begins by analyzing the memory requirements for a 256M x 128 memory system, calculating the number of RAM chips needed, the number of address bits, and the memory banks. The assignment then explores instruction formats, determining the number of bits required for opcodes and registers, and the largest unsigned binary number representable in a memory word. Furthermore, the solution examines different addressing modes, including immediate, direct, indirect, and indexed addressing, by tracing the execution of an 'Add' instruction with varying memory contents and register values. Finally, the solution presents assembly code implementations for the expression A = (B + C) * (D - E) on 2-, 1-, and 0-address machines, demonstrating how the same computation can be performed with different instruction set architectures.

Running head: ORGANIZATION AND ARCHITECTURE
Computer Organization and Architecture
[Student Name]
[University Name]

1
ORGANIZATION AND ARCHITECTURE
1. Suppose that a 256M * 128 Memory built using 1024 K *32 RAM Chips
and memory is word addressable. [10 marks]
a. How many RAM Chips are necessary?
256M*128 = (256*1024*128)kb
Total number is required (256 * 1024 * 128)/(32 * 1024) = 1024
b. How many RAM Chips are there per memory word?
256 M = 256*1024*8 bits
ram chip capacity = (32*1024)
total (256 * 1024 * 8)/(32 * 1024) = 64 RAM chip are required
c. How many address bits are needed for each RAM Chip?
Required RAM chip = 1024 = 2^30
So, 30 is required
d. How many banks will this memory have?
256/32 = 8 banks
e. How many address bits are needed for all memory?
1024/32 = 32 address bit is needed

2
ORGANIZATION AND ARCHITECTURE
2. A digital computer has a memory unit with 48 bits per word. The
instruction set consists of 240 different operations. All instructions have an
operation code part (opcode) and an address part (allowing for only one
address). Each instruction is stored in one word of memory. [2+2+2 = 6
marks].
a. How many bits are needed for the opcode?
16 bits.
b. How many bits are needed to specify the register? How many bits are left for the
address part of the instruction?
32 bits required. The left bit will depend on the users.
c. What is the largest unsigned binary number that can be accommodated in one
word of memory?
2^48 -1.
3. Consider an instruction Add 1000. Memory contents, Accumulator (AC),
and R1 Register contents are depicted in the below figure: (such as memory
address 1000 contains a value 1400, memory address 1100 contains a value
400 etc. All the numbers used here are decimals.)
i) Immediate
1000+500 = 1500 and this will be stored in accumulator

3
ORGANIZATION AND ARCHITECTURE
ii) Direct
1400+500 = 1900 which will be stored in accumulator
iii) Indirect
1300 + 500 =1800 which is loaded from accumulator
iv) Indexed
1000 + R1 = 1200
The value of 1200 is 1000. So the value will be 1000+500 = 1500
4. Write code to implement the expression: A= (B + C) * (D - E) on 2-, 1- and
0-address machines. In accordance with programming language practice,
computing the expression should not change the values of its operands.
2 – addressing machine
MOV R1, B
ADD R1, C
MOV R2, D
SUB R2, E
MUL R1, R2
MOV A, R1
1 – addressing machine
LOAD B

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ORGANIZATION AND ARCHITECTURE
ADD C
STORE T
LOAD D
SUB E
MUL T
STORE A
0 - addressing machine
PUSH B
PUSH C
ADD
PUSH D
PUSH E
SUB
MUL
POP A