Computer Architecture Homework: Binary to Floating-Point Conversion

This assignment solution addresses three key areas within computer architecture. Task 1 involves converting a binary number to its floating-point representation, detailing the process of determining the sign, exponent, and mantissa, ultimately arriving at the decimal equivalent. Task 2 focuses on Boolean algebra, presenting a Boolean expression, its minimization, and a corresponding diagram, along with a proof using Boolean identities. The final task, Task 3, delves into memory organization, calculating the number of RAM chips required given specifications, determining the number of bits needed for various memory operations, and demonstrating the execution of instructions using different addressing modes (immediate, direct, indirect, and indexed), including the conversion of an expression into different instruction formats (two-address, one-address, and zero-address).

Task 1.
a. Convert the binary number to floating number
0 Number is
positive
+
01111110 Exponent (0*27) +
(1*26) +
(1*25) +
(1*24) +
(1*23) +
(1*22) +
(1*21) +
(1*20)
= 126
= 126 –
127
= -1
10100000000000000000000 Mantissa 1.101 1.101 *
10-
1
= 0.1101
= 0.1101
= (1*2-1) + (1*2-2) + (0*2-3) + (1*2-4)
= 1/2 + 1/4 + 1/16
= 0.8125
b. 1. Signed magnitude: 01111 to 11111
-15 to +15
2. One's complement: 10000 to 01111
-16 to +15
3. Two’s complement: 10001 to 01111
-17 to +15
Task 2.
a) Let Clock timing denoted by A
Let the Switch denoted by B
Let the Gate denoted by C
Boolean Expression:
C = A.B
Minimisation:
For minimisation, let the switch (B) be always on, then the status for gate is
always dependent on the clock timing (A).
C = A

Diagram:
b) X’Y + XYZ’ + Y’ + XZ (Y+Y’) = 1
Consider the L.H.S to prove the Boolean expression.
X’Y + XYZ’ + Y’ + XZ (Y+Y’)
= X’Y + XYZ’ + Y’ + XZ.1
= X’Y + (XZ’ + Y’) (Y + Y’) + XZ
= X’Y + (XZ’ + Y’).1 + XZ
= X’Y + XZ’ + Y’ + XZ
= X’Y + Y’ + X (Z’ + Z)
= (X’ + Y’) (Y + Y’) + X.1
= (X’ + Y’).1 + X
= X’ + Y’ + X
= 1 + Y’
= 1
Hence Proved.
Identities used
 Inverse law: A + A’ = 1
 Distributive law: A + BC = (A + B) (A + C)
 Identity law: A.1 = A
 Null law: A + 1 = 1
Task 3.
1. Memory – 256M * 128
RAM chips – 1024K * 32
Memory is word addressable
a) No. of Rows  256∗210∗210
210∗210 = 256
No. of Columns  128
32 = 4
b) 4 RAM chips (equal to the no. of the columns)
c) 1204K = 220
20 bits are needed for each RAM chip.
d) 256 banks (equal to the no. of the rows)
A
B
C = A.B

e) 256M = 228
28 its are needed for all memory.
2. 48 bits per word
240 different operations.
a) For 240 operations, we cannot use 7 bits as 27 = 128 which cannot
accommodate 240 operations.
Therefore, 8 bits are needed. 28 = 256.
b) We know, as this is one address instruction, so no register is mentioned.
48bits = Opcode bits + Address bits
Address bits = 48 – 8
Address bits are 40.
c) Largest unsigned binary number  248 – 1
3. Instruction: Add 1000
a) Immediate addressing mode:
AC = 1000 + 500
= 1500
b) Direct addressing mode:
AC = [1000] + 500
= 1400 + 500
= 1900
c) Indirect addressing mode:
AC = [[1000]] + 500
= [1400] + 500
= 1300 + 500
= 1800
d) Indexed addressing mode:
AC = [1000 + R1] + 500
= [1000 + 200] + 500
= [1200] + 500

= 1000 + 500
= 1500
4. Expression: A = (B+C) * (D-E)
a) 2 – address instructions
LOAD R1, B
ADD R1, C
LOAD R2, D
SUB R2, E
MUL R1, R2
STORE A, R1
b) 1 – address instructions
LOAD B
ADD C
STORE TEMP
LOAD D
SUB E
MUL TEMP
STORE A
c) 0 – address instructions
PUSH B
PUSH C
ADD
PUSH D
PUSH E
SUB
MULT
STORE A