University Name - Computer Organization and Architecture Assignment

This assignment solution covers key concepts in computer organization and architecture, including memory calculations, instruction formats, and addressing modes. The solution addresses specific questions related to calculating storage capacity, rotational delay, and access time for a storage device. It also explores the breakdown of instruction formats, determining the number of bits required for opcodes, registers, and addresses. Furthermore, the assignment delves into the design of instruction sets, calculating the number of instructions for different addressing modes (2-address, 1-address, and 0-address) and providing examples of assembly code sequences for various arithmetic operations. This comprehensive solution is a valuable resource for students studying computer architecture.

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Assignment 2: MARIE & ISA
[Student Name]
[University Name]

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Answer to question 1
We can calculate the total number of Track which is 512*23 = 11776
And total number of sectors is 64*11776 = 753664
Therefore, we can get -
I) Total capacity = 753664*32 = 24117248 bytes = 23 GB
II) Rotational delay = (1 / (RPM / 60)) * 0.5 * 1000 = 3.125 ms
III) Access time = seek time + rotational delay = 10+3.125 ms = 13.125 ms
Answer to question 2
I) 8 bits are needed for the opcode.
ii) 2^3 = 8. So, 3 bits are needed for specify the register.
iii) 32-8 = 24. Total 24 bits are left for the address part of the instruction.
iv) The maximum allowable size of the memory is 2^24
v) 232-1 is the largest unsigned binary number that can be accommodate in on word of
memory.
Answer to question 3
Total number of address instruction is 213 = 8192
FIVE 2-address instruction is = 5 * 25 * 25 = 5120
TWENTY 1-address instruction is = 20 * 25 = 640
The possible 0-address instruction that can be accommodate for the instruction set
architecture is = 8192 – (5120+640) = 2432.

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Answer to question 4
2-address 1-address 0-address
MOV C, X
ADD C, Y
MOV B, Y
SUB B, Z
MPY C, B
MOV D, X
MPY D, Y
DIV C, D
LOAD X
ADD Y
STORE A
LOAD Y
SUB Z
MPY A
STORE A
LOAD X
MPY Y
DIV A
STORE A
PUSH X
PUSH Y
ADD
PUSH Y
PUSH Z
SUB
MPY
PUSH X
PUSH Y
MPY
DIV
POP A