Computer Architecture Assignment: Addressing Modes & Instructions

This document presents a comprehensive solution to a computer architecture assignment, focusing on instruction set design and addressing modes. The solution begins by calculating the number of instructions supported based on the instruction length and address field size, considering two-address, one-address, and zero-address instruction formats. The assignment then demonstrates the implementation of a given set of arithmetic operations (P=X+Y, Q=Y-Z, R=X*Y) using different instruction sets: two-address, one-address, and zero-address machines. For each instruction set, the solution provides the sequence of instructions required to perform the operations, demonstrating the differences in how data is accessed and manipulated. References to relevant literature such as "Digital Design and Computer Architecture" by Harris & Harris, and other research papers, are also included to support the analysis and provide further context.

Running Head: COMPUTER ARCHITECTURE 1
Computer Architecture
Institution
Date
Name

COMPUTER ARCHITECTURE 2
Question 3
Length of instruction = 13 bits
Address field size = 5 bits.
Two address instructions = 5
One address instructions = 20
Maximum instruction code represented utilizing 13 bits = 2^13 = 8192
And the address field size is 5 bits therefore, each address will contain 2^5 Possible value
= 32
2-Address instruction will require 32*32 address space. But we have 5 such instructions.
Thus 5*32*32 = 5120
The 1-Address instruction will require 32 address space but we have 20 instructions.
Thus 20*32 = 640
The number of 0-address instructions to accommodate therefore is:
The total – (2 Address instr + 1 Address instr) (Harris & Harris, 2015)
8192- (5120+640)
8192-5760
= 2432

COMPUTER ARCHITECTURE 3
Question 4
Take:
P=X+Y
Q=Y-Z
R=X*Y
Then, A= P ×Q
R
2 Machine instruction: - Two address machine holds one source operand and destination
operand using the register.
MOV T1, X
ADD T1, Y
MOV P, T1
MOV T2, Y
SUB T2, Z
MOV Q, T2
MOV T3, X
MUL T3, Y
MOV R, T3

COMPUTER ARCHITECTURE 4
MOV T4, P
MUL T4, Q
DIV T4, R
MOV A, T4
1 machine instruction: - One address machines will hold one source operand and the
destination operand using the accumulator (Stanley, Doggett, Cook & Fairclough, 2016)
LOAD X
ADD Y
STORE P
LOAD Y
SUB Z
STORE Q
LOAD X
MUL Y
STORE R
LOAD P

COMPUTER ARCHITECTURE 5
MUL Q
DIV R
STORE A
0 address machine instruction: - Zero address machine will store source and destination
operands using stack (Chu, 2014).
PUSH X
PUSH Y
ADD
POP P
POP Y
PUSH Y
PUSH Z
SUB
POP Q
POP X
PUSH X

COMPUTER ARCHITECTURE 6
POP Y
PUSH Y
MUL
POP R
PUSH P
PUSH Q
MUL
PUSH R
DIV
POP A
POP A
References
Chu, Y. (Ed.). (2014). High-level language computer architecture. Academic Press.
Harris, S., & Harris, D. (2015). Digital Design and Computer Architecture: ARM Edition.
Morgan Kaufmann.
Stanley, T. D., Doggett, D., Cook, L., & Fairclough, D. (2016). Simple emulated computer
improvements to facilitate understanding in introductory computer programming and

COMPUTER ARCHITECTURE 7
computer organization/architecture classes. Journal of Computing Sciences in Colleges,
31(4), 56-62.