Computer Architecture Coursework: MIPS Assembly and Pipeline Analysis

This assignment solution addresses two problems related to computer architecture. The first problem requires converting C code that calculates a histogram of marks into equivalent MIPS assembly code, including initializing counters, looping through an array, and implementing conditional statements. The second problem focuses on pipeline analysis, requiring the student to trace instruction execution through a 5-stage MIPS pipeline, identify stall cycles, and determine if data hazards exist in given instruction sequences. The solution provides detailed explanations and analyses of pipeline behavior, including forwarding and hazard detection, demonstrating a comprehensive understanding of computer architecture principles. This assignment is a coursework for the Faculty of Science, Engineering and Computing, assessing the student's ability to write assembly code and understand how pipelining improves efficiency.

Faculty of Science, Engineering and Computing
Assessment Form
Coursework Aim
This exercise will allow you to writing programs in the language of the computer and understand
how pipelining improves efficiency by executing multiple instructions simultaneously.
Module learning outcomes assessed in this piece of coursework
This assessment is designed to assess your ability in the following module learning outcomes:
 Describe and differentiate between the essential features and operations of modern
computer architectures
Submission details
Submission of coursework will be performed using Turnitin on StudySpace.
Coursework brief
The assignment consists of two problems that you need to solve during the module workshops. Both
have equal weights. (The problems are given at the end of this Assessment Form). You should submit
an individual written report that provides the answers and a related discussion for each problem.
Assessment criteria
The assessment grade boundaries for both problems are shown overleaf.
Feedback (including details of how and where feedback will be provided)
During the computer architecture workshop series you will work on formative worksheet exercises
covering the skills and competences you will need for this coursework. Before moving onto the next
exercise you should show your work to the workshop tutors and discuss your solutions. This
feedback is essential to tackling the (summative) coursework. As we progress through the exercises,
models solutions will be presented during the workshop along with a discussion of the typical errors
students make and methods for mitigating these. In addition to the feedback and advice during
workshops, generic feedback will be presented shortly after the completion of each exercise. Each
student will also receive short written feedback on their specific submission.

Table 3 Criteria Grades for the Computer Organisation Coursework
Problem 1
Weight
Exceeded
Expectations
Met Expectations Close to expectations Below Expectations
100-80% 79-60% 59-40% 39-1%
Q1
50%
Working code that
produces the
expected results. Well
documented. Uses
the write syntax of
the assembly
language based on
the lecture notes.
MIPS instruction if
possible correctly
used. Uses the
correct way of
accessing memory
locations.
Code that does not
give the expected
results, but method
used is correct. Well
documented. Uses
the write syntax of
the assembly
language based on
the lecture notes.
MIPS instruction if
possible correctly
used. Uses the
correct way of
accessing memory
locations.
Code that does not
give the expected
results. Method is not
fully correct. Well
documented. Uses
the write syntax of
the assembly
language based on
the lecture notes.
MIPS instruction if
possible correctly
used. Not using the
correct way of
accessing memory
locations.
Failure to understand
key concepts of
translating high level
code to assembly
code which form an
important principle of
the computer
architecture topic.
Problem 2
Weight
Exceeded
Expectations
Met Expectations Close to expectations Below Expectations
100-80% 79-60% 59-40% 39-1%
Q2
20%
Correct answer
showing the required
stalling / no stalling
with justification.
Correct answer
showing the required
stalling / no stalling
with no justification.
Not Correct answer,
but correct method
used with
justification.
Failed to provide the
correct answer.
Q3
30%
Correct answer
showing the required
stalling / no stalling
with justification.
Correct answer
showing the required
stalling / no stalling
with no justification.
Not correct answer
showing the required
stalling / no stalling
with justification.
Failed to provide the
correct answer
showing the required
stalling / no stalling
with justification.

Assessment Problems
Problem 1 (50%)
The C-code shown below will loop through an array of marks (integer values between 0 and 100) and
calculate a histogram of these marks.
(50 marks)
int A, B, C, D, F; // declare grade counters
int i; // declare loop counter
int N ; // Number of scores to analyse
A=0; B=0; C=0; D=0; F=0; // initialize grade counters
// Read in test scores into grades array?
// N will be equal to the number of grades
// assume N = 50
for (i=0; i<N; i++) {
if(scores[i] >= 90)
A = A + 1;
else if(scores[i] >= 80)
B = B + 1;
else if(scores[i] >= 70)
C = C + 1;
else if(scores[i] >= 60)
D = D + 1;
else
F = F + 1;
}
Q1 Write the equivalent MIPS assembly code for the C-code shown above.
You should assume the following:
- The number of scores, N, to be analysed is 50.
- The address of the first element in the marks array is contained in $s0.
Additionally, to make it easier for you to keep track of register assignments, you may use
register names that have the same name as the variable names used in the code above. For
example, to initialize the register that holds the A counter, you might write:
add $A, $0, $0
If you do choose to use actual MIPS register names, you should write your code out as follows
i.e. with appropriate comments:
add $t0, $0, $0 # $t0 maps to variable A; we need to initialize it to 0
Problem 2: (50%)
This problem consists of two questions Q1 and Q2 which consider the basic MIPS 5-stage pipeline (F,
D, EX, M, WB). You should assume that there is full forwarding.
Q2 Show how the instructions below proceed through the pipeline and indicate many stall cycles
occur. You should assume the beq instruction is taken. Use the following chart.
(30 marks)

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
lw $1, 0($2)
add $2, $2,
$2
sub $2, $2,
$1
beq, $2, $2,
X
lw $1, 4($2)
X: add $2,
$2, $1
Q3 Assume the following sequence of instructions is executed in a traditional 5-stage pipeline.
Does the lw / add instruction combination represent a data hazard? If so, why? If not, why
not?
(20 marks)
lw $5, 4($6)
sub $6, $5, $10
add $7, $6, $5