Computer Architecture: CPU Cache, Memory Design, and TLB Assignment

This assignment delves into several key aspects of computer architecture. It begins with a problem involving a CPU's physical address space and requires the student to demonstrate the contents of the cache using a two-way set associative mapping with an LRU replacement policy and determine the hit rate. Next, the assignment involves designing a memory module using specific memory ICs, calculating the number of ICs needed, the number of address lines, and the size of the decoder, culminating in a memory diagram. Finally, the assignment presents a scenario involving virtual memory, requiring the student to determine the number of bits in the virtual address, the number of pages, the number of bits required for the physical address, and the number of frames. The student is then tasked with calculating physical addresses, and identifying whether each address generates a TLB hit, a page table hit, or a page fault.

Solution:
1. A CPU has 6 bits physical address and generates addresses 00,01, 0E, 0F,01,18,19and 3E in
Hex.
A. Show the contents of the cache using two way set associative mapping, assume LRU
replacement policy.
Ans.
B. What is hit rate?
Ans. Hit rate = 1 / 8

6. Design a memory module of 2 Mbytes of memory using 256K of memory IC
a. How many memory ICs will need?
Ans. We need 8 memory ICs.
b. How many address lines will have each IC?
Ans. Each IC has 18 address lines
c. What is the size of the decoder?
Ans. Size of decoder is 3 to 8
d. show the diagram of the memory

4. A computer has128Kbytes of virtual memory , 64 Kbytes of main memory and page size of
8k bytes.Following figure shows TLB and page table of the computer.
1. How many bits is virtual address
Ans. There are 17 (13+4) bits in virtual address
2. How many pages are in virtual memory
Ans. No. of pages = 128 / 8 = 16 pages
3. How many bits require for physical address
Ans. There are 16 (10+6) bits in physical address
4. How many frames (blocks) are in main memory
Ans. No. of frames = 64 kB / 8 kB = 8 frames
5. Following virtual addresses are given, find physical addresses and identify if each address
generates TLB Hit , Page table Hit or page fault
Address TLB Hit Page Table Hit Page fault Physical address
1C586 1 1 0 7C586
05976 1 1 0 65976
10676 1 1 0 70676
TLB
Page table Page frame V
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
110
111
101
---
001
100
-----
-----
----
-----
000
-----
----
----
-----
-----
1
1
1
0
1
1
0
0
0
0
1
0
0
0
0
0
TLB
Page Number Frame Number
1110 011
0111 010