University of XYZ: Computer Organization and Architecture Assignment 2

This document presents a solution to a Computer Organization and Architecture assignment. The assignment explores the MARIE assembly language, including the implementation of a Fibonacci sequence generator and the analysis of its limitations. It also delves into instruction set architecture (ISA), calculating the number of possible zero-address instructions based on given parameters. Furthermore, the solution provides assembly code examples for different addressing modes (3-address, 2-address, 1-address, and 0-address machines) to perform arithmetic operations. The assignment is a comprehensive overview of fundamental computer architecture concepts, providing insights into assembly language programming, instruction set design, and addressing techniques. The solution showcases the student's understanding of these core principles through detailed explanations and code examples.

Running head: COMPUTER ORGANIZATION AND ARCHITECTURE
Assignment 2: MARIE and ISA
Name of the Student
Name of the University
Author’s Note

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COMPUTER ORGANIZATION AND ARCHITECTURE
Table of Contents
Answer to Question 1:.....................................................................................................................2
Answer to Question 2:.....................................................................................................................5
Answer to Question 3:.....................................................................................................................6
Bibliography....................................................................................................................................8

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COMPUTER ORGANIZATION AND ARCHITECTURE
Answer to Question 1:
1.a.
The MARIE program is created for the calculation of the Fib (n) where user inputs is n and is
given below -
ORG 100
Input Input number
Store N // Take user input for printing the number of terms
Store Ctr // Stores the variable of the counter to the accumulator
Loop1, Clear
Load Ctr // The value stored on the accumulator is loaded to the processor.
Subt C1 // A substraction is done with the value of C1
Store Ctr
Load F2 // The value of F2 is loaded on the accumulator
Add F1 // An addition of F1 is done with the F2
Store F3 // The value of the addition is stored in F3 on the accumulator
Load F1 // The value of F1 is loaded on the accumulator
Store F2 // The value of F2 is stored on accumulator
Load F3

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COMPUTER ORGANIZATION AND ARCHITECTURE
Store F1
Load Ctr
Skipcond 400 // A condition is applied for skipping the check condition
Jump Loop1 // JUmp is applied for jumping to the location 400
Load Ctr
Output
Load N // The Output value is N
Output
Load F1 // Final value of the output is displayed
Output
Halt // used for controlling the halts
N, DEC 0
Ctr, DEC 0
C1, DEC 1
F1, DEC 0
F2, DEC 1
F3, DEC 0

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COMPUTER ORGANIZATION AND ARCHITECTURE
1.b.
For n > 24 the program would not produce a correct result and this is checked by
gradually increasing the value of n and identification of the output.
The maximum value for which the program can produce the correct result is 24 because
the threshold limit for the integer can be crossed with the system and there is a storage limit for
each of the data type are used for the analysis of the source code.

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COMPUTER ORGANIZATION AND ARCHITECTURE
Answer to Question 2:
Number of possible instruction set for the 11 bits address = 211
= 2048
Number of encoding consumed by the two-address instructions = 6 × 24 × 24
= 1536
Number of encoding taken by the one-address instructions = 30 × 24
= 480
Therefore the possible number of zero-address instructions = 2048 − (1536 + 480)

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COMPUTER ORGANIZATION AND ARCHITECTURE
= 32 instructions.
Answer to Question 3:
For the 3 Address Machine
ADD R1, B, C
SUBT R2, D, E
MUL A, R1, R2
For the 2 Address Machine
LOAD R1, B
ADD R1, C
LOAD R2, D
SUBT R2, E
MULT R2, R1
STORE A, R2
For the 1 Address machine
LOAD B
ADD C
STORE TEMP
LOAD D

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COMPUTER ORGANIZATION AND ARCHITECTURE
SUBT E
MULT TEMP
STORE A
For the 0 address machine
PUSH B
PUSH C
ADD
PUSH D
PUSH E
SUB
MULT
STORE A

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COMPUTER ORGANIZATION AND ARCHITECTURE
Bibliography
Null, L., & Lobur, J. (2014). The essentials of computer organization and architecture. Jones &
Bartlett Publishers.
Wu, J., Li, L., & Wu. (2016). Advanced Computer Architecture. Springer Singapore.