Computer Org. & Architecture Homework: Conversions & Circuit Design

This document presents a detailed solution to a computer organization and architecture homework assignment. The solution covers various aspects of data conversion, including binary, hexadecimal, and decimal conversions, as well as two's complement representation and IEEE754 single-precision format. It also addresses the design and implementation of logic circuits using universal gates like NAND and NOR, along with the minimization of Boolean functions using truth tables and Karnaugh maps. The document includes a logic diagram and its corresponding minimized Boolean expression, demonstrating the application of Boolean algebra to simplify complex digital circuits. The solution is supplemented with a bibliography referencing relevant academic resources.

Running head: COMPUTER ORGANIZATION AND ARCHITECTURE
Computer Organization and Architecture
Name of Student-
Name of University-
Author’s Note-

1COMPUTER ORGANIZATION AND ARCHITECTURE
Answer to Question 1:
a. (2ED1)16 to Binary
(2ED1)16= (0010 1110 1101 0001)2
b. −29.6610 to Binary
Firstly, converting 29.66 to binary, we get
(29.66)10 = (11101.101010001111010111)2
Since, the number is negative
Two’s complement is to be done for getting the binary number
So, −29.6610 = (00010.010101110000101001)
c. 1001111001102 to Hexadecimal
(1001 1110 0110) = (9E6)16
d. 11101110 (8-bit 2’s complement representation) to decimal
= 11101110 to decimal is 18
Since, the number given has 1 on the MSB bit, so the number after conversion is (-18)
e. 1 01111110 11000000000000000000000
The MSB 1 shows that the number will be negative.
01111110 in binary will be 126 is the exponent. The bias is 127.

2COMPUTER ORGANIZATION AND ARCHITECTURE
11000000000000000000000 will be 0.75 is the fraction
(-1)sign bit * (1+fraction) * 2 exponent – bias
So, the decimal number will be (-1)sign bit * (1.075) *2126-127 = -0.875
Answer to Question 2:
a. There are two universal gates NAND gate and NOR gate. The NAND gate is
represented as the complement of AND gate. NOR gate comprises of NOT gate and OR gate.
Using the NAND gate inverter that can be made is shown below.
b. The expression for the circuit is stated below:
QAJ + QA’J + Q’AJ + QAJ’ = P
 QA (J + J’) + J (QA’ + Q’A) = P
 QA + J (Q XOR A) = P
The logic diagram for this above circuit is

3COMPUTER ORGANIZATION AND ARCHITECTURE
Answer to Question 3:
X Y Z X ⨁Y YZ (X⨁ Y
⨁ ZY)’
(Z.Y)' X ⨁Y
⨁ ZY
⨁ ZY’
X. X ⨁
Y
F
1 1 1 0 1 0 0 1 0 1
Minimized Boolean expression is
{(X + Y) ⨁ (YZ) ⨁ (YZ)’}’ + X . X ⨁ Y

4COMPUTER ORGANIZATION AND ARCHITECTURE
Bibliography
Collier, C. P., Wong, E. W., Belohradský, M., Raymo, F. M., Stoddart, J. F., Kuekes, P. J., ... &
Heath, J. R. (1999). Electronically configurable molecular-based logic
gates. Science, 285(5426), 391-394.
Huang, Y., Duan, X., Cui, Y., Lauhon, L. J., Kim, K. H., & Lieber, C. M. (2001). Logic gates
and computation from assembled nanowire building blocks. Science, 294(5545), 1313-
1317.
Neamen, D. A. (2001). Electronic circuit analysis and design(Vol. 2). McGraw-Hill.