Memory Interleaving and Prime Number Program - Assignment

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Added on  2022/12/18

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Homework Assignment
AI Summary
This assignment delves into the concept of memory interleaving, a crucial aspect of computer architecture. It begins with a MARIE assembly code program designed to check if a given integer is a prime number. The assignment then explores the core topic of memory interleaving, defining and differentiating between high-order and low-order interleaving techniques. High-order interleaving is explained with examples, showing how the highest-order bits of an address specify the memory block or bank. Similarly, low-order interleaving is discussed, where the lower-order bits determine the memory block. The assignment provides concrete examples, such as a 4-way interleaving system and an 8-way interleaving setup, illustrating how memory is divided into banks and locations. Finally, the assignment analyzes a scenario involving 32 memory chips, detailing how bits are utilized for bank and location selection in a 32-way memory interleaving system, further solidifying the understanding of memory organization and addressing.
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Running Head: MEMORY INTERLEAVING 1
Memory Interleaving
Institution
Date
Name
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2MEMORY INTERLEAVING
Question 2.
Write a MARIE program.
Assembly Code to check for Prime number;
.LC0:
.string "Enter an integer to check whether it is prime or
not."
.LC1:
.string "%d"
.LC2:
.string "%d Result is 1.\n"
.LC3:
.string "%d Results is 0.\n"
main:
push rbp
mov rbp, rsp
sub rsp, 16
mov edi, OFFSET FLAT:.LC0
call puts
lea rax, [rbp-8]
mov rsi, rax
mov edi, OFFSET FLAT:.LC1
mov eax, 0
call scanf
mov eax, DWORD PTR [rbp-8]
mov edi, eax
call check_prime(int)
mov DWORD PTR [rbp-4], eax
cmp DWORD PTR [rbp-4], 1
jne .L2
mov eax, DWORD PTR [rbp-8]
mov esi, eax
mov edi, OFFSET FLAT:.LC2
mov eax, 0
call printf
jmp .L3
.L2:
mov eax, DWORD PTR [rbp-8]
mov esi, eax
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3MEMORY INTERLEAVING
mov edi, OFFSET FLAT:.LC3
mov eax, 0
call printf
.L3:
mov eax, 0
leave
ret
check_prime(int):
push rbp
mov rbp, rsp
mov DWORD PTR [rbp-20], edi
mov DWORD PTR [rbp-4], 2
.L9:
mov eax, DWORD PTR [rbp-20]
cmp eax, DWORD PTR [rbp-4]
jle .L6
mov eax, DWORD PTR [rbp-20]
cdq
idiv DWORD PTR [rbp-4]
mov eax, edx
test eax, eax
jne .L7
mov eax, 0
jmp .L5
.L7:
add DWORD PTR [rbp-4], 1
jmp .L9
.L6:
mov eax, DWORD PTR [rbp-4]
cmp eax, DWORD PTR [rbp-20]
jne .L10
mov eax, 1
jmp .L5
.L10:
.L5:
pop rbp
ret
Screenshots;
Prime Number
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4MEMORY INTERLEAVING
Non-Prime Number
Question 3.
a) Explain with an example of what is meant by high-order interleaving and low-
order interleaving in memory organisation.
The process by which one has to split memory into a bank/blocks is called
memory interleaving (Psaropoulos, et al., 2019).
High Order Interleaving:
Where the highest order bit in address specifies the memory block or bank. Then
the remaining bits will specify the location in that memory block.
Example; When you have a 4-way interleaving- 4 banks available and its memory
size is 16*8 thus every memory block has 4 addresses.
Lower Order Interleaving;
In this case, The lower order bit represents the memory block and the higher
order bit represents the location in the specific block.
Example;
When Memory is given 32*8 and its 8 way interleaving therefore every memory
block has (32/8) locations.In order to detect 8 banks of memory, we require 2^3 =8
(3bits) and every bank contains 4 locations, and thus we need 2^2 =4 ) 2 bits for that
location in that memory bank.
B) .
Memory of 32 4k*8 bit chips;
This is 32-way memory interleaving (32 banks, 4k * 8 ) thus each memory bank
has 4096 bytes.
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5MEMORY INTERLEAVING
5 bits are utilized for memory bank (2^5 =32) and 12 bits used for location in the
memory block(2^12=4096) all 17 bit addresses.
When in high order, interleaving, 5 bits at first are used to select the memory
bank and the remaining 12 its are utilized for location (Gaud et al., 2015).
Low Order
High Order
References
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6MEMORY INTERLEAVING
Gaud, F., Lepers, B., Funston, J., Dashti, M., Fedorova, A., Quéma, V., ... & Roth, M.
(2015). Challenges of memory management on modern NUMA
systems. Communications of the ACM, 58(12), 59-66.
Psaropoulos, G., Legler, T., May, N., & Ailamaki, A. (2019). Interleaving with
coroutines: a systematic and practical approach to hide memory latency in index
joins. The VLDB Journal, 28(4), 451-471.
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