Computer Architecture and Organization Homework Solution Analysis

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Homework Assignment
AI Summary
The assignment provides comprehensive solutions to various problems related to computer architecture, focusing on the calculation of the number of RAM chips needed for different memory configurations. It details how 30 address bits are necessary per RAM chip due to a requirement for 2^30 addresses, and explains that with 1024 RAM chips, 8 memory banks are required because each bank consists of 32 such chips. For addressing modes, it describes immediate, direct, indirect, and indexed methods with calculations showing how values are added or stored in an accumulator based on given addresses. The assignment further converts operations between different types of addressing machines (2-addressing to 1-addressing to 0-addressing) using stacks for the latter. The bibliography includes various scholarly sources related to computer science theories and hardware design.
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Running head: COMPUTER ARCHITECTURE AND ORGANIZATION
Computer Architecture and Organization
Name of the Student:
Name of the University:
Author Note
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COMPUTER ARCHITECTURE AND ORGANIZATION
Answer to question 1
a. We need 256 Kbytes, i.e., 256 x 1024 x 128 bits.
We have RAM chips of capacity 32 Kbits = 32 x 1024 bits.
Number of Ram chips required are (256 * 1024 * 128)/(32 * 1024) = 1024
b. We need 256 Kbytes, i.e., 256 x 1024 x 8 bits.
We have RAM chips of capacity 32 Kbits = 32 x 1024 bits.
Number of Ram chips required are (256 * 1024 * 8)/(32 * 1024) = 64
c. Number of RAM chips required are 1024 = 2^30.
Hence address bits needed for each RAM chip required are 30.
d. The number bits present in the RAM = 1024
Hence the number of memory banks required for this system are: 256/32 = 8
e. Address bits required for all memory = 1024/32 = 32
Answer to question 2
a. Number of bits for the opcode = 16.
b. Number bits required for the registers = 8
Number of bits required for addresses = 16
c. The largest unsigned binary number: 2^48 -1.
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COMPUTER ARCHITECTURE AND ORGANIZATION
Answer to question 3
i) Immediate
Value of Add 1000 in immediate addressing is 1000 + 500 = 1500 and the Value is stored in the
accumulator.
ii) Direct
Value of Add 1000 in direct addressing mode is 1400 + 500 =1900.
iii) Indirect
Value of 1000 is 1400. The value of address 1400 is 1300. Hence 1300 + 500 =1800 is loaded
into the accumulator.
iv) Indexed
1000 + R1 = 1200
The value located in 1200 is 1000. Hence the value loaded in the accumulator would be 1000 +
500 = 1500.
Answer to question 4
2 – addressing machine
MOV R1, B
ADD R1, C
MOV R2, D
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COMPUTER ARCHITECTURE AND ORGANIZATION
SUB R2, E
MUL R1, R2
MOV A, R1
1 – addressing machine
LOAD B
ADD C
STORE T
LOAD D
SUB E
MUL T
STORE A
0 - addressing machine
PUSH B
PUSH C
ADD
PUSH D
PUSH E
SUB
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COMPUTER ARCHITECTURE AND ORGANIZATION
MUL
POP A
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COMPUTER ARCHITECTURE AND ORGANIZATION
Bibliography
Chen, J., Huang, Y., Fu, B., & Li, J. (2013). MacWilliams identity for m-spotty weight
enumerators over finite rings. J. Comput. Inform. Syst, 9(4), 1565-1574.
Chen, Y. H., & Liu, Y. Y. (2013, March). Dual-addressing memory architecture for two-
dimensional memory access patterns. In Proceedings of the Conference on Design,
Automation and Test in Europe (pp. 71-76). EDA Consortium.
Giurgiutiu, V., & Lyshevski, S. E. (2016). Micromechatronics: Modeling, analysis, and design
with MATLAB. CRC Press.
Huang, Z., & Safie, F. (2016, January). Addressing uniqueness and unison of reliability and
safety for a better integration. In Reliability and Maintainability Symposium (RAMS),
2016 Annual (pp. 1-7). IEEE.
Mano, M. M. (2017). Digital logic and computer design. Pearson Education India.
Marwedel, P., & Goossens, G. (Eds.). (2013). Code generation for embedded processors (Vol.
317). Springer Science & Business Media.
Tanenbaum, A. S. (2016). Structured computer organization. Pearson Education India.
Venkat, A., & Tullsen, D. M. (2014, June). Harnessing ISA diversity: Design of a
heterogeneous-ISA chip multiprocessor. In Computer Architecture (ISCA), 2014
ACM/IEEE 41st International Symposium on (pp. 121-132). IEEE.
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