Computer Architecture and Organization - Assignment Solution

This assignment solution addresses key concepts in computer architecture and organization. Question 1 explores number system conversions between bases (binary, octal, hexadecimal, and base-3), and determines the range of values representable in one's complement, two's complement, and signed magnitude formats. Question 2 delves into interrupts, their role in computer systems, and methods for handling multiple interrupts, including hardware and software interrupts, and the distinction between multiple bus and single bus architectures. The assignment demonstrates a clear understanding of data representation, number system conversions, and the fundamental principles of computer architecture.

Running head: COMPUTER ARCHITECTURE AND ORGANIZATION
Computer Architecture and Organization
Name of Student-
Name of University-
Author’s Note-

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Question 1:
a) (152)b = 0x6A
Step 1: (0x6A)16 = 6 * 161 + 10 * 160 = 96 + 10 = 106 which is not equal to the given
question
Step 2: (0x6A)16 = (01 101 010)2 = (152)8
So the value of b = 8
Step 1: In the first step, the hexadecimal number is converted to decimal number which
does not give the and as provided in the question.
Step 2: In step 2, the hexadecimal number is converted to binary number and taking three
digits from right side it gives the octal number of the hexadecimal number. So the base of the
given question is 8.
b) Conversions
i)0xBAD into 3-base representation
Step 1: (BAD)16 = B * 162 + A * 161 + D * 160 = (2989)10
Step 2: (2989)10 = 2989 mod 3 = 1
996 mod 3 = 0
332 mod 3 = 2
110 mod 3 = 2
36 mod 3 = 0

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12 mod 3 = 0
4 mod 3 = 1
1 mod 3 = 1
So, (BAD)16 = (11002201)3
Step 1: In first step, the hexadecimal number is converted to decimal number by
multiplying 160 at units place, 161 at tenth’s place and so on.
Step 2: In step 2, the decimal number is then converted to base 3 by performing modulus
with 3, and the get the result in bottom up approach.
ii) (321)7 into 2-base (binary) representation
Step 1: (321)7 = 3 * 72 + 2 * 71 + 1 * 70 = (162)10
Step 2: (162)10 = 162 mod 2 = 0
81 mod 2 = 1
40 mod 2 = 0
20 mod 2 = 0
10 mod 2 = 0
5 mod 2 = 1
2 mod 2 = 0
1 mod 2 = 1
So, (321)7 = (10100010)2

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Step 1: In first step, the seven base number is converted to decimal number by
multiplying 170 at units place, 171 at tenth’s place and so on.
Step 2: In step 2, the decimal number is then converted to binary by performing modulus
with 2, and the get the result in bottom up approach.
iii) (123)5 to octal representation
(123)5 = 123 mod 8 = 6
4 mod 8 = 4
(123)5 = (46)8
Description: The base 5 number is operated with modulus 8 and the result is obtained
from in bottom up approach.
iv) (21.21)8 into decimal representation
(21.21)8 = 2 * 81 + 1 * 80 + 8-1 * 2 + 1 * 8-2
= 17 + 0.25 + 0.015625
= 17.265625
Description: The octal number is converted to decimal number by multiplying 80 at units
place, 81 at tenth’s place and the decimal part is multiplied by 8-1 at units place, 8-2 at tenth’s place
and the result is obtained.
c) i) One’s Compliment
Highest value = 3

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Formula: + (2n-1 – 1), where n = 3
Lowest value = - 3
Formula: - (2n-1 – 1), where n = 3
ii) Two’s Compliment
Highest value = + 3
Formula: + (2n-1 – 1), where n = 3
Lowest value = - 4,
Formula: - (2n-1), where n = 3
ii) Signed Magnitude
Highest value = + 3
Formula: + (2n-1 – 1), where n = 3
Lowest value = - 3
Formula: - (2n-1 – 1), where n = 3
Question 2
a) Interrupt is particularly a signal that comes from a particular device that are attached to
a particular computer system or from a program which requires to stop the operating system and
also figure out what can be done next. When there are input and output devices that are ready for
transferring the input and output transfer, then only interrupt is generated in a computer system
(Tanenbaum, 2016). The processing unit of the system mainly receives the signal, the stops the

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instruction that was being processed and runs the current instruction on an emergency basis. The
main concept included in defining priority in all the devices to set their priority is done by a
system known as interrupt priority system. All the personal computers are interrupt driven.
Interrupt driven computer consists of one particular program that includes a list of computer lists
in a single program. One computer instruction is performed at a time in a single computer. But
the instruction can be interrupted and so that it can perform other important tasks and this is
known to be as multitasking. A particular operation system includes some code that includes
interrupt handler. This helps to prioritize the interrupts as well as helps them to save the
interrupts in a queue is more waiting is handled. There is another program known as the
scheduler that schedules the program that is to be done next.
There are two types of interrupts; hardware interrupts and software interrupts. Hardware
interrupts mainly occurs when there is an input and output operation is being completed in a
system that includes reading data from the tape drive in a computer system (Achermann et al.,
2017). Software interrupts mainly occurs at the time when the application program requests or
terminates some services from a particular operating system. In a system, interrupt hardware
request has high value that are associated with the particular device. Trap is another type of
interrupt that is basically generated by the CPU to send a message that states there is some error
in the system or there is some condition that has occurred that needs assistance from OS that is
needed.
Two approaches that are used for handling multiple interrupts are: disabling the interrupts
when another interrupt is being processed and second approach is defining the priorities for all
the interrupts and process that interrupt that has the highest priority (Dumas, 2016). For the first
case, when a process is processed in the system, all other interrupts that comes to the system gets

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disabled until the running process is finished. This works as first come first serve basis. The
processes are handled in a sequential manner. For the econ case, the priority of the interrupt is set
according to their arrival and those interrupts will only be processed irrespective of the first
come first serve basis.
b) The benefits of multiple bus architecture compared with single bus architecture are
stated below:
Speed and efficiency: In a single bus architecture, all the components that includes the
CPU, computer peripherals, and the computer memory are shared through a common bus (Kusic,
2018). When there are many devices in a computer system that needs bus at same time, in a
single bus architecture it creates a conflict that is referred as bus contention. In a single bus
architecture, time is wasted which also decreases the speed as well as efficiency of the system.
Expansion: In a multiple bus architecture, there is more number of choices available
compared to single bus architecture (Comer, 2017). This is not possible in single bus
architecture. With multiple bus architecture, more number of devices can be connected with the
system which expands the number of processes that can be carried out in a system.
Compatibility: The multiple bus architecture helps the system to be compatible that is it
helps to connect with all other new types of components in the system. Multiple architecture of
bus helps to connect the legacy equipment that includes printers, and all other old hard drives
that are included in the system.
Multi-core: In a single CPU there are many heavy demand for the bus which carries the
memory data and all the peripheral traffic for the hard drives, printer and the networks
(Achermann et al., 2017). To make all the cores in the system in an active status, multiple

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architecture of bus is used for increasing the total amount of information from the system and in
to the system of microprocessor. This helps to keep the waiting time in a minimum position.

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