Computer Organization and Architecture Assignment - Analysis

This document presents a comprehensive solution to a Computer Organization and Architecture assignment. The solution addresses several key concepts, including calculating drive capacity, rotational delay, and access time. It also delves into instruction set architecture, determining the number of bits required for opcodes and register specifications, and calculating the maximum memory size. The assignment further explores different addressing modes, providing examples of three-address, two-address, one-address, and zero-address instructions, demonstrating their functionality with code snippets. Finally, the document includes a bibliography of relevant resources for further study in computer organization and architecture.

Running head: COMPUTER ORGANIZATION AND ARCHITECTURE
Computer Organization and Architecture
Name of the Student
Name of the University
Author’s Note

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COMPUTER ORGANIZATION AND ARCHITECTURE
Answer to Question 1:
I. The capacity of the drive –
Capacity = surfaces * Tracks * Sectors * Bytes
= 23 * 512 * 64 * 32
= 23 Gb
II. Rotational Delay –
Rotation delay = ½ * [ (60/ RPM) * (1000 / 1 Sec)]
= ½ * [(60 / 9600) (1000)]
= 6.25 / 2
= 3.125 ms
III. Access Time –
Access time = Seek time + latency
= 10 ms + 3.125 ms
= 13.125 ms
Answer to Question 2:
I. Bits required for the opcode is 2 ^8 > 232
Thus, 8 bits of opcode
II. Bits needed for the specification of the register is 2^3 = 8
Thus 3 bits are required for specification of the register
III. Bits left for the address part of the instruction is 32- 8 = 24
IV. Maximum allowable size of memory is 2^24

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COMPUTER ORGANIZATION AND ARCHITECTURE
V. Largest unsigned binary number which can be accommodated in one word of
memory is 2^32-1
Answer to Question 3:
Total number of address instruction = 2^13
= 8192
5 2-address = 5 * 2^5 * 2^5
= 5120
20 1-address = 20 *2^5
= 640
Therefore, Number of 0 address instruction still possible = 8192- (5120+640)
= 2432
Answer to Question 4:
Three Address instruction
ADD R1, X, Y R1  M [X] + M [Y]
SUBT R2, X, Y R2  M [X] – M [Y]
MUL R3, X, Y R3  M [X] * M[Y]
MUL A, R1, R2, R4 R4 R1 * R2
DIV A, R3 M [X]  R4 / R3
Two Address instruction

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COMPUTER ORGANIZATION AND ARCHITECTURE
MOV R1, X R1  M [X]
ADD R1, Y R1  R1 + M [Y]
MOV R2, Y R2  M [X]
SUBT R2, Z R2  R2 – M [Z]
MOV R3, X R3  M [X]
MUL R1, R2 R1  R1 * R2
DIV R1, R3 R1  R1 / R3
MOV A, R1 M [A]  R1
One Address instruction
LOAD X AC M [X]
ADD Y AC  A [Z] + M [Y]
STORE T M [T]  AC
LOAD Y AC  M [Y]
SUBT Z AC  AC - M [Z]
MUL T AC  AC * M [T]
STORE T M [T]  AC
LOAD X AC M [X]
MUL Y AC  AC * M [Y]

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COMPUTER ORGANIZATION AND ARCHITECTURE
DIV AC AC  AC / M [T]
STORE A M [A]  AC
Zero Address Instruction
PUSH X TOS  X
PUSH Y TOS  Y
ADD TOS  (X+Y)
PUSH Y TOS  Y
PUSH Z TOS  Z
SUB TOS  (Y - Z)
PUSH X TOS  X
PUSH Y TOS  Y
MUL TOS  (X * Y)
MUL TOS  (X+Y) * (Y - Z)
DIV TOS  (X+Y) * (Y - Z) / (X * Y)
POP A M [A]  TOS

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COMPUTER ORGANIZATION AND ARCHITECTURE
Bibliography
Harris, S., & Harris, D. (2015). Digital Design and Computer Architecture: ARM Edition.
Morgan Kaufmann.
Levy, H. M. (2014). Capability-based computer systems. Digital Press.
Levy, H., & Eckhouse, R. (2014). Computer programming and architecture: The VAX. Digital
Press.
Null, L., & Lobur, J. (2014). The essentials of computer organization and architecture. Jones &
Bartlett Publishers.
Patterson, D. A., & Hennessy, J. L. (2017). Computer Organization and Design RISC-V Edition:
The Hardware Software Interface. Morgan kaufmann.
Prasad, P. W. C., Alsadoon, A., Beg, A., & Chan, A. (2016). Using simulators for teaching
computer organization and architecture. Computer Applications in Engineering
Education, 24(2), 215-224.
Tanenbaum, A. S. (2016). Structured computer organization. Pearson Education India.
Torrellas, J. (2016). Extreme-scale computer architecture. National Science Review, 3(1), 19-23.