Computer Organization and Architecture Assignment Solution

This document presents a comprehensive solution to a computer organization and architecture assignment. It begins by addressing memory organization, calculating the number of RAM chips required for a specified memory size and word length, and determining the number of address bits and memory banks. The assignment then delves into instruction set architecture, calculating opcode bits, register bits, and address bits within an instruction word. The document also examines different addressing modes (immediate, direct, indirect, and indexed) by analyzing the contents of memory, the accumulator, and registers. Finally, it concludes by providing assembly code implementations for a given arithmetic expression on 2-address, 1-address, and 0-address machines. The solution includes a bibliography of relevant academic sources.

Running head: ORGANIZATION AND ARCHITECTURE
Organization and Architecture
Name of the Student:
Name of the University:
Author Note

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ORGANIZATION AND ARCHITECTURE
1. Suppose that a 256M * 128 Memory built using 1024 K *32 RAM Chips
and memory is word addressable. [10 marks]
a. How many RAM Chips are necessary?
We need 256 Kbytes, i.e., 256 x 1024 x 128 bits.
We have RAM chips of capacity 32 Kbits = 32 x 1024 bits.
Number of Ram chips required are (256 * 1024 * 128)/(32 * 1024) = 1024
b. How many RAM Chips are there per memory word?
We need 256 Kbytes, i.e., 256 x 1024 x 8 bits.
We have RAM chips of capacity 32 Kbits = 32 x 1024 bits.
Number of Ram chips required are (256 * 1024 * 8)/(32 * 1024) = 64
c. How many address bits are needed for each RAM Chip?
Number of RAM chips required are 1024 = 2^30.
Hence address bits needed for each RAM chip required are 30.
d. How many banks will this memory have?
The number bits present in the RAM = 1024
Hence the number of memory banks required for this system are: 256/32 = 8
e. How many address bits are needed for all memory?
Address bits required for all memory = 1024/32 = 32

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ORGANIZATION AND ARCHITECTURE
2. A digital computer has a memory unit with 48 bits per word. The
instruction set consists of 240 different operations. All instructions have an
operation code part (opcode) and an address part (allowing for only one
address). Each instruction is stored in one word of memory. [2+2+2 = 6
marks].
a. How many bits are needed for the opcode?
16 bits would be required for the opcode part of the word.
b. How many bits are needed to specify the register? How many bits are left for the
address part of the instruction?
32 bits would be left for addressing and the register parts. This can be manipulated
according to the requirements of the users.
c. What is the largest unsigned binary number that can be accommodated in one
word of memory?
The largest unsigned binary number that can be accommodated in one word of the
memory are: 2^48 -1.

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ORGANIZATION AND ARCHITECTURE
3. Consider an instruction Add 1000. Memory contents, Accumulator (AC),
and R1 Register contents are depicted in the below figure: (such as memory
address 1000 contains a value 1400, memory address 1100 contains a value
400 etc. All the numbers used here are decimals.)
Assuming R1 is implied in the indexed addressing mode, determine the actual
value loaded into the accumulator (AC) using the following addressing modes:
i) Immediate
Value of Add 1000 in immediate addressing is 1000 + 500 = 1500 and the Value is stored in the
accumulator.
ii) Direct
Value of Add 1000 in direct addressing mode is 1400 + 500 =1900 and the value is stored in
Accumulator.
iii) Indirect
Value of 1000 is 1400. The value of address 1400 is 1300. Hence 1300 + 500 =1800 is loaded
into the accumulator.
iv) Indexed
The value of ADD 1000 would provide the following results.
1000 + R1 = 1200
The value located in 1200 is 1000. Hence the value loaded in the accumulator would be 1000 +
500 = 1500.

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ORGANIZATION AND ARCHITECTURE
4. Write code to implement the expression: A= (B + C) * (D - E) on 2-, 1- and
0-address machines. In accordance with programming language practice,
computing the expression should not change the values of its operands.
2 – addressing machine
MOV R1, B
ADD R1, C
MOV R2, D
SUB R2, E
MUL R1, R2
MOV A, R1
1 – addressing machine
LOAD B
ADD C
STORE T
LOAD D
SUB E
MUL T
STORE A
0 - addressing machine

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ORGANIZATION AND ARCHITECTURE
PUSH B
PUSH C
ADD
PUSH D
PUSH E
SUB
MUL
POP A

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ORGANIZATION AND ARCHITECTURE
Bibliography
Agmon Ben-Yehuda, O., Posener, E., Ben-Yehuda, M., Schuster, A., & Mu'alem, A. (2014,
March). Ginseng: Market-driven memory allocation. In ACM SIGPLAN Notices (Vol. 49,
No. 7, pp. 41-52). ACM.
Berger, E. D., Zorn, B. G., & McKinley, K. S. (2013). OOPSLA 2002: Reconsidering custom
memory allocation. ACM SIGPLAN Notices, 48(4S), 46-57.
Darte, A., Isoard, A., & Yuki, T. (2016, March). Extended lattice-based memory allocation.
In Proceedings of the 25th International Conference on Compiler Construction (pp. 218-
228). ACM.
Tanenbaum, A. S. (2016). Structured computer organization. Pearson Education India.