Computer Organization Homework: Addressing & Instruction Sets

This document presents a comprehensive solution to a computer organization assignment. It begins by determining the required bits for an opcode and memory size based on the number of instructions. The solution then delves into various addressing modes, including immediate, direct, indirect, and indexed addressing, providing detailed calculations for each. Furthermore, the assignment explores the implementation of a given expression (F = (A-B) * (C*D+E)) using different machine architectures: 0-address, 1-address, and 2-address machines, demonstrating the differences in instruction sets. Finally, the solution calculates the number of instructions obtainable from a specific address bit size, considering different instruction formats. A bibliography of relevant sources is also included.

Running head: COMPUTER ORGANIZATION
Computer Organization
Name of the Student:
Name of the University:
Author Note

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COMPUTER ORGANIZATION
Answer to question number 1
1. There are 199 instructions. Hence 2^8 instructions would be required as 2^7 = 128.
Hence 8 bits for the opcode is required.
2. Number bits left for the address part of the instruction = 24 – 8 = 16 bits.
3. The maximum allowable size of the memory = 2^16 bits.
4. 24 1s or (2^24) -1 is the highest word that can be allocated in the memory.
Answer to question number 2
1. Immediate Addressing mode
The value to be added to the accumulator is 900
The value already stored in the accumulator is 200.
Therefore, the value which is loaded in the accumulator = 900 + 200 = 1100
2. Direct Addressing Mode
Effective address is 900
The value to be added to the accumulator is 1000.
The value already stored in the accumulator is 200.
Therefore, the value which is loaded in the accumulator = 1000 + 200 = 1200
3. Indirect Addressing mode
The effective address of 900 is 1000.
The value to be added to the accumulator is 500.
Value in the accumulator is 200.
Therefore, the value which is loaded in the accumulator = 500 + 200 = 700
4. Indexed Addressing mode
The value of base register is 100.
The effective address therefore = 900 + 100 = 1000.

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COMPUTER ORGANIZATION
The value in location 1000 = 500
Value in the accumulator is 200.
Therefore, the value which is loaded in the accumulator = 500 + 200 = 700
Answer to question number 3
The expression provided: F = (A-B) *(C*D+E)
0-Address Machine
PUSH C
PUSH D
MUL
PUSH E
ADD
PUSH A
PUSH B
SUB
MUL
POP F
1-Address Machine
LOAD A
SUB B
STORE T1

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COMPUTER ORGANIZATION
LOAD C
MUL D
ADD E
STORE T2
LOAD T1
MUL T2
STORE F
2-Address Machine
MOV T1, A
SUB T1, B
MOV T2, C
MUL T2, D
ADD T2, E
MUL T1, T2
MOV F, T1
Answer to question number 4
The number of instructions set which can be obtained from 10 bits of address = 2^10
= 1024

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COMPUTER ORGANIZATION
Number of bits taken by 2 address instructions: 15 x (2^3) x (2^3) = 960
Number of bits taken by 1 address instructions: 7 x (2^3) = 56
Number of bits available for 0 address instructions: 1024 – (960 + 56) = 8

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Bibliography
Asghar, Z., & Ali, U. (2016). COMPARATIVE ANALYSIS OF MULTIPROCESSOR
ARCHITECTURE. International Journal of Advanced Research in Computer
Science and Electronics Engineering (IJARCSEE), 5(12), pp-131.
Dekeyser, J. L., & Aljendi, A. S. (2015, June). Adopting new learning strategies for computer
architecture in higher education: case study: building the S3 microprocessor in 24
hours. In Proceedings of the Workshop on Computer Architecture Education (p. 6).
ACM.
Farooq, S. M., & Basha, S. S. (2016, January). A study on Fibonacci series generation
algorithms. In Advanced Computing and Communication Systems (ICACCS), 2016
3rd International Conference on (Vol. 1, pp. 1-5). IEEE.
Levy, H. M. (2014). Capability-based computer systems. Digital Press.
Null, L., & Lobur, J. (2014). The essentials of computer organization and architecture. Jones
& Bartlett Publishers.
Prinz, P., Crawford, T., Hennessy, J. L., & Patterson, D. A. (2018). Computer Architecture: A
Quantitative Approach.
Skiba, M. A., Sikkema, A. P., Fiers, W. D., Gerwick, W. H., Sherman, D. H., Aldrich, C. C.,
& Smith, J. L. (2016). Domain organization and active site architecture of a
polyketide synthase C-methyltransferase. ACS chemical biology, 11(12), 3319-3327.
Tanenbaum, A. S. (2016). Structured computer organization. Pearson Education India.
Veldhorst, M., Eenink, H. G. J., Yang, C. H., & Dzurak, A. S. (2017). Silicon CMOS
architecture for a spin-based quantum computer. Nature communications, 8(1), 1766.

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Wang, S., & ZHANG, C. (2016). Computer architecture.