Computer Information System: IEEE 754, Overflow, and Memory

This assignment solution covers key concepts in computer information systems, focusing on number representation and memory organization. It includes a step-by-step conversion of the decimal number 1025.25 into its IEEE 754 32-bit representation, detailing the sign bit, exponent, and mantissa. The solution also addresses overflow detection in binary addition using 4-bit numbers and sign extension techniques. Furthermore, it explores memory addressing schemes using RAM chips, including calculations for addressable memory locations and chip selection. The document provides detailed explanations and numeric results for each question, covering topics like decoder design and the impact of temporal and spatial locality on cache performance. Desklib is a platform where students can find similar solved assignments and study resources.

Running head: COMPUTER INFORMATION SYSTEM
Computer Information System
Name of Student-
Name of University-
Author’s Note-

1COMPUTER INFORMATION SYSTEM
Question 1:
a. 1025.25
Step 1: Since the number is positive. The LSB bit will be 0
Step 2: Converting them as a sum, we get
210 + 20 + 2-2 = 1025.24
As binary the sum can be written as: 10000000001.01
Step 3: Getting the exponent, we get
1.000000000101 x 210
Significant of the number- 00000000010100000000000
Step 4: Since the exponent is 10, so 127 + 10 = 137
As a sum it can be written as: 128 + 8 + 1
As binary it can be written as: 10001001
Step 5: Sign Exponent Significant
0 10001001 00000000010100000000000
b. The result is 0 00000000 0000110111

2COMPUTER INFORMATION SYSTEM
Question 2:
a. The result given in the question has an overflow 1 as the LSB bit of the result. While
performing the addition, the LSB bit of the two number is 1+ 1 which has overflow 1.
b. Sign extend of 1001to 6 bit is 110111
Sign extend of 1010 to 6 bit is 110110
Addition of 110111 and 110110 is 01101101
The result has stack overflow as 01.
Question 3:
a. Decoder with 4 input is shown below:
2 to 4 bit binary decoders is a 4 input decoder

3COMPUTER INFORMATION SYSTEM
b. 256 x 8 bit RAM
i) Since the memory has 256 x 8 bit RAM, so the address memory location of the
memory 28 = 256 memory address.
There are total of 128 chips. S, the total number of addressable memory is 128 x 256 =
32768 memory address.
ii) For each byte of memory there are 256 bits of memory address for addressing each
byte of memory.
iii) With 256 x 8 bit RAM there are 8 address lines for each chip select.
iv) The address line that are needed to select the memory location on a chip is 256
address lines.
c. i) The total memory location that are addressable are 64 x 128 = 8192 address.
ii) The bits that will be used for chip select is 1111 and the bits for identifying the word is
10101001.
d. Temporal Locality mainly helps to determine the sensitivity to the cache size and the
spatial locality mainly helps to determine the sensitivity of the size of the line. Generally spatial
gets exploited when larger blocks of cache are used and also incorporates mechanisms of
prefetching that fetches items of the anticipated use in the control logic of cache.

4COMPUTER INFORMATION SYSTEM
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