Data Logic Representation: Number Conversion and Circuit Proof

This assignment solution delves into the fundamental concepts of data logic representation, addressing key areas such as number system conversions and logic gate equivalency. The solution begins by determining the base 'x' for a given equation involving hexadecimal and an unknown base. It then performs conversions between different number systems, including hexadecimal to base-3, base-7 to binary, decimal to octal, and base-8 to decimal. The assignment further explores the representation of positive and negative numbers using one's complement, two's complement, and signed magnitude methods within a 3-bit computer. Additionally, the solution provides a proof of equivalence for two combinational circuits and demonstrates the minimization of a logic circuit using Boolean algebra and De Morgan's laws. The document concludes by proving a Boolean algebra expression. Desklib offers a wealth of similar solved assignments and resources for students.

Running head: DATA LOGIC REPRESENTATION
Data Logic Representation
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1DATA LOGIC REPRESENTATION
Answer for Question 1:
a) Given (152) x= (6A) 16
 X2 + (5 * X1) + (2 * X0) = (6 * 161) + (10 * 160)
 X2 + 5X + 2 = 106
 X2 + 5X - 104 = 0
 X2 + 13X - 8X – 104 = 0
 X(X + 13) – 8(X + 13) = 0
 (X - 8) (X + 13) = 0
 X = 8 and X = -13
Since, X cannot be negative; so X is 8
(152)8= (6A) 16
b) i) BED = (B * 162) + (E * 161) + (D * 160)
= 2816 + 224 + 13
= (3053)10
(3053)10 =
Divider Dividend Remainder
3 3053 2
3 1017 0
3 339 0
3 113 2
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2DATA LOGIC REPRESENTATION
3 37 1
3 12 0
3 4 1
1
BED16 = (11012002)3
ii) (321)7 = (3 * 72) + (2 * 71) + (1 * 70)
= (162)10
So, (162)10 =
Divider Dividend Remainder
2 162 0
2 81 1
2 40 0
2 20 0
2 10 0
2 5 1
2 2 0
1
(162)10 = (10100010)2
iii) Conversion
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3DATA LOGIC REPRESENTATION
Divider Dividend Remainder
8 1235 3
8 154 2
8 19 3
2
So, (1235)10 = (2323)8
iv) For given 21.218 = (2 * 81) + (1 * 80). (2 * 8-1) + (1 * 7=8-2)
= 17 + 0.25 + 0.015625
= 17.265625
Hence, (21.21)8 = 17.265625
c) i) One’s compliment –ve no= 100
One’s compliment +ve no = 100
ii) Two’s compliment –ve no = 101
Two’s compliment +ve no = 011
iii) Signed magnitude –ve no = 111
Signed magnitude +ve no = 011
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4DATA LOGIC REPRESENTATION
Answer to Question 2:
a) For proving both the circuits, following steps are taken
A B C D
0 0 0 1
0 1 0 1
1 0 0 1
1 1 1 0
For R.H.S.
A B C D E
0 0 1 1 1
0 1 1 0 1
1 0 0 1 1
1 1 0 0 0
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5DATA LOGIC REPRESENTATION
So, output of L.H.S. circuit is equal to output of the R.H.S.
Hence, both the circuits are equal.
b)
The above circuit can be minimized by the following steps
(A' . B') + (A . B)
= A'B' + AB
= ((AB)'(A'B')’)' … From De Morgan’s theorem
= ((A' + B')(A + B))' … From Distributive Law
= (A'A + B'A + A'B + B'B)'
= (1 + AB' + A'B + 1)'
= (AB' + A'B)'
= (A ^ B)' that is A XNOR B
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6DATA LOGIC REPRESENTATION
c) X’ + Y’ + XYZ’
= X’ + Y’ + (X’ + Y’ + Z)’ [Stated from De-Morgan’s Law]
= (XY (X’ + Y’ + Z))’ [Stated from De-Morgan’s Law]
= (XX’Y + XYY’ + XYZ)
= (0 + 0 + XYZ)
= (XYZ)’
= X’ + Y’ + Z’ [Stated from De-Morgan’s Law]
= X’ + Y’ + XYZ’ = X’ + Y’ + Z’
[HENCE, PROVED]
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7DATA LOGIC REPRESENTATION
Bibliography
Harris, S., & Harris, D. (2015). Digital Design and Computer Architecture: ARM Edition.
Morgan Kaufmann.
Wang, S., & ZHANG, C. (2016). Computer architecture.
Impagliazzo, J., Pow-Sang, J. A., Trejos, I., Meier, R., & Nunes, D. J. (2017, March). Latin and
American perspectives on the computer engineering (CE2016) report. In World Engineering
Education Conference (EDUNINE), IEEE (pp. 9-13). IEEE.
Tanenbaum, A. S. (2016). Structured computer organization. Pearson Education India.
Comer, D. (2017). Essentials of computer architecture. CRC Press.
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