University Data Representation, Boolean Algebra and Circuit Design

This assignment solution covers fundamental concepts in data representation and digital logic. It begins with an analysis of number systems, including one's complement, two's complement, signed magnitude, and unsigned magnitude representations, along with conversions between binary, octal, decimal, and hexadecimal systems. The solution then delves into Boolean algebra, simplifying and proving logical expressions using distributive laws and truth tables. Furthermore, it includes a truth table analysis for a scenario involving assignments, blogs, discussion forums, and quizzes, leading to the derivation of a minimized Boolean expression and the corresponding circuit diagram. The assignment concludes with a bibliography of relevant sources, including academic publications on digital logic, computer design, and related topics. This resource provides a comprehensive understanding of data representation and logic design principles.

Running head: DATA REPRESENTATION
Data Representation
Name of Student-
Name of University-
Author’s Note-

1DATA REPRESENTATION
Answer to Question 1.
(a).
I. The computer that has word size of 8 bits has one’s compliment range of -127 to 127.
II. The computer that has word size of 8 bits has two’s compliment range of -128 to 127.
III. The computer that has word size of 8 bits has signed magnitude of range of -127 to 127.
IV. The computer that has word size of 8 bits has unsigned magnitude of range of 0 to 255.
(b).
I. (5AB)16 = (2356)8
II. (101101.101)2 = (45.625)10
III. (12348)10 = (1100000111100)2
IV. (679810)10 = (133223220)5
V. (976.6310)10 = (1111010000.10100)2
VI. (1001001011)2 = (24B)16
VII. (10011110) = -(98)10
Answer to Question 2:
(a) X’(X+Y)+(XX+Y)(Y’+X)=Y+X
L.H.S. – X’(X+Y) + XXY’+ XXX+ YY’+ XY [Because of Distributive law]
= X’X + X’Y + XXY’+ XXX + YY’+ XY [Because of Distributive law]
= 0 + X’Y + XY’ + X + 0 + XY [Since, X’X = 0 AND XX = X]
= X’Y + XY’ + X + XY
= X’Y + XY’ + X (1 + Y)
= X’Y + XY’ + X [Since, 1 + Y = 1]

2DATA REPRESENTATION
= X’Y + X (Y’ + 1)
= (X + X’) (X + Y)
= (X + Y) [Since, X + X’ = 1] = R.H.S.
(b) Suppose, Assignment, Blog, Discussion Forum and Quiz of the student’s test be A, B, C,
and D and let P be passing possibility of the student.
Therefore, the truth table will be:
A B C D P
0 0 0 0 0
0 0 0 1 0
0 0 1 0 0
0 0 1 1 0
0 1 0 0 0
0 1 0 1 0
0 1 1 0 0
0 1 1 1 0
1 0 0 0 0
1 0 0 1 0
1 0 1 0 0
1 0 1 1 1
1 1 0 0 0
1 1 0 1 1
1 1 1 0 1
1 1 1 1 1

3DATA REPRESENTATION
The expression of the following table will be
AB’CD + ABC’D + ABCD’ + ABCD
After minimizing the above equation we get,
A [D (B’C + BC’) + BC]
Circuit diagram for the above equation is
Figure 1: Circuit Diagram

4DATA REPRESENTATION
Bibliography
Bouvier, C., & Zimmermann, P. (2014). Division-Free Binary-to-Decimal Conversion. IEEE
Transactions on Computers, 63(8), 1895-1901.
Kempthorne, D., & Steele, A. (2014). An evaluation of different delivery methods for teaching
binary, hex and decimal conversion. Journal of Applied Computing and Information
Technology, 18(2), 2014.
Mano, M. M. (2017). Digital logic and computer design. Pearson Education India.
Roy, S., & Setua, S. K. (2016). Arithmetic of 5th Generation Computer.
Smolka, G. (2014). Boolean Logic.
Zhang, T., Cheng, Y., Guo, J. Z., Xu, J. Y., & Liu, X. J. (2015). Acoustic logic gates and
Boolean operation based on self-collimating acoustic beams. Applied Physics
Letters, 106(11), 113503.