Computer Org & Architecture: Data Representation and Digital Logic

This assignment focuses on data representation and digital logic within the context of computer organization and architecture. It includes problems related to base conversion, including converting between decimal, hexadecimal, octal, and binary number systems. The assignment also covers different methods of representing signed numbers, such as one's complement, two's complement, and signed magnitude, and explores the range of values that can be represented with a limited number of bits. Furthermore, it requires simplifying and analyzing combinational logic circuits using Boolean algebra and De-Morgan's Law to demonstrate the equivalence of different circuit implementations. Desklib offers this solution, along with a wealth of other resources, to aid students in their studies.

Running head: COMPUTER ORGANIZATION AND ARCHITECTURE
Computer Organization and Architecture
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1COMPUTER ORGANIZATION AND ARCHITECTURE
Question 1:
a) (152) x= (6A) 16
 X2 + (5 * X1) + (2 * X0) = (6 * 161) + (10 * 160)
 X2 + 5X + 2 = 106
 X2 + 5X - 104 = 0
 X2 + 13X - 8X – 104 = 0
 X(X + 13) – 8(X + 13) = 0
 (X - 8) (X + 13) = 0
 X = 8 and X = -13
Therefore, value of X is 8.
(152)8= (6A) 16
b) i) The value BED = (B * 162) + (E * 161) + (D * 160)
= 2816 + 224 + 13
= (3053)10
(3053)10 =
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2COMPUTER ORGANIZATION AND ARCHITECTURE
BED16 = (11012002)3
ii) (321)7 = (3 * 72) + (2 * 71) + (1 * 70)
= (162)10
Again, (162)10 =
(162)10 = (10100010)2
iii) Conversion
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3COMPUTER ORGANIZATION AND ARCHITECTURE
(1235)10 = (2323)8
iv) 21.218 = (2 * 81) + (1 * 80). (2 * 8-1) + (1 * 7=8-2)
= 17 + 0.25 + 0.015625
= 17.265625
(21.21)8 = 17.265625
c) i) Lowest number of one’s compliment = 100
Highest number of one’s compliment = 100
ii) Lowest number of two’s compliment = 101
Highest number of two’s compliment = 011
iii) Lowest number of signed magnitude = 111
Highest number of signed magnitude = 011
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4COMPUTER ORGANIZATION AND ARCHITECTURE
Question 2:
a) After generating the output of L.H.S.
A B C D
0 0 0 1
0 1 0 1
1 0 0 1
1 1 1 0
After generating the output of R.H.S.
A B C D E
0 0 1 1 1
0 1 1 0 1
1 0 0 1 1
1 1 0 0 0
So, L.H.S. is equal to R.H.S.
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5COMPUTER ORGANIZATION AND ARCHITECTURE
b) The part of this circuit can be given minimized as
Can be represented by
So, the finalized circuit is
c) X’ + Y’ + XYZ’
= X’ + Y’ + (X’ + Y’ + Z)’ [Deriving De-Morgan’s Law]
= (XY (X’ + Y’ + Z))’ [Deriving De-Morgan’s Law]
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6COMPUTER ORGANIZATION AND ARCHITECTURE
= (XX’Y + XYY’ + XYZ)
= (0 + 0 + XYZ)
= (XYZ)’
= X’ + Y’ + Z’ [Deriving from De-Morgan’s Law]
= X’ + Y’ + XYZ’ = X’ + Y’ + Z’ [HENCE, PROVED]
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