Assignment 1 - ITC544: Data Representation and Digital Logic Analysis

This document presents a complete solution to Assignment 1 for ITC544, focusing on data representation and digital logic. The solution includes the conversion of a binary number to a floating-point number, detailing the steps and calculations involved. It also addresses the analysis of a 5-bit word, exploring signed magnitude, one's complement, and two's complement representations. Furthermore, the assignment tackles a practical application involving a gate control system, defining the boolean expression, minimization, and a diagram for the system. Finally, the document provides a proof of a boolean expression using identities. This comprehensive solution helps students understand and solve complex problems in data representation and digital logic.

Name:
Student ID:
Subject Code: ITC544
Assessment No.: Assignment 1
Assessment Name: Data Representation and Digital
Logic
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1.
a. Convert the binary number to floating number
0 01111110 10100000000000000000000
The first bit from the left represents the sign bit, as it is 0, therefore, the number is a
positive number.
The 2 – 9 bits from the left represents the exponent of the number. Here, it is
01111110.
(0*27) + (1*26) + (1*25) + (1*24) + (1*23) + (1*22) + (1*21) + (1*20)
= 0 + 64 + 32 + 16 + 8 + 4 + 2 + 0
= 126
 126-127 = -1
 Therefore, the exponent is -1.
The 10 – 31 bits from the left represents mantissa of the number. Here, it is
10100000000000000000000
 1.101
 (1.101) * 10-1 # this is the number
= 0.1101
= (1*2-1) + (1*2-2) + (0*2-3) + (1*2-4)
= ½ + ¼ + 1/16
= 0.8125
As the number is positive, therefore, the floating number is 0.8125
b. Word of “5 bits”
Binary Decimal
Signed magnitude 01111 to 11111 -15 to +15
One's complement 10000 to 01111 -16 to +15
Two’s complement 10001 to 01111 -17 to +15
2.
a. In this, the switch of the gate and 24-hour timing clock concurrently result to the
opening and closing of the main entrance door.
If the switch is on, it will result 1 else 0. Similarly, for 24-hour timing clock if the
time is 9.00 to 12.00 or 13.00 to 16.00, it will result in 1, else 0.
The values of both the inputs “and’ed” to result the gate status.
Boolean expression:
Switch – S
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Clock – C
Gate Status – R
R = S.C
Minimisation:
The Boolean expression R = S.C is already in its minimized form, therefore, no
further minimization is required. But if, we remove the switch and assume that the
switch will be always on for the simplicity, then the Main Gate status will depend
only on the time.
R = C
Diagram:
b. Prove that
X’Y + XYZ’ + Y’ + XZ (Y+Y’) = 1
L.H.S Identities used
X’Y + XYZ’ + Y’ + XZ (Y+Y’)
X’Y + XYZ’ + Y’ + XZ.1 A + A’ = 1
X’Y + XYZ’ + Y’ + XZ A.1 = A
(X’+Y’)(Y+Y’) + XYZ’ + XZ AB + C = (A+C)(B+C)
(X’+Y’).1 + XYZ’ + XZ A+A’ = 1
X’+Y’+XYZ’+XZ A.1 = A
(X’+X)(X’+Z) + (Y’+Y)(Y’+XZ’) AB + C = (A+C)(B+C)
1.(X’+Z) + 1.(Y’+XZ’) A+A’ = 1
X’+Z+Y’+XZ’ 1.A = A
(X’+X)(X’+Z’) + Z + Y’ A + BC = (A+B)(A+C
1.(X’+Z’)+Z+Y’ A+A’ = 1
X’ + Z’ + Z + Y’ 1.A = A
X’ + 1 + Y’ A + A’ = 1
1 A + 1 = 1
=R.H.S
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