CEN 211: Digital Logic Design I - Digital Clock Design Project

This assignment presents a comprehensive solution for a digital clock design project, addressing the requirements of CEN 211 at King Saud University. The project involves designing a 12-hour digital clock using Logisim software. The solution details the implementation of mod-10 and mod-6 counters, explaining their functionality and integration with 7-segment displays. The design optimizes the circuit for gate input cost and includes the use of T flip-flops. The document also describes the reset mechanism, which ensures the clock resets to 12:00:00. The solution includes a detailed explanation of the clock's operation, including the role of enable signals and the display of hours, minutes, and seconds on the HEX LED display. The document provides a complete, step-by-step guide to designing a digital clock, making it a valuable resource for students studying digital logic design.

Introduction
The digital clock makes use of two types of counters. The mod 10 counter and mod 6 counter. The
mod 10 counters are connected to count units’ value for seconds, minutes and hour. The mod 6
counters are used to count tens place value for seconds and minute values. The ten’s value for hour
is counted using single T flip flop.
The reset circuit causes the clock to return o initial value of all 0 when ever clock reaches the count
of 12:00:00.
Mod 10 counter are 4 bit counters built using 4 T flip flops and reset circuit that reloads counter to 0
when it reaches count of 10. So counter only counts value from 0 to 9. As it rollovers from 9 to 0. It
also generates a signal that is used to enable the next stage counter. Similar structure is used for
mod 6 counter, but it only counts from 0 to 5 and rollovers at 5. Both of the counters are connected
alternately in a cascaded manner.
Mod -10 Counter.
Enable signal allows the counter to count up on each incoming clock. If enable is held low. The clock
will not increment the counter. Secondly if counter reaches a value of 1010, the reset signal is
generated internally to reset the counter to 0. Next signal is generated when counter is enabled and
has reached it’s maximum value 9 in case of mod 10 counter.

Mod-6 counter
The counter is smaller version of mod 10 counter. If counter reaches a value of 110, the reset signal
is generated internally to reset the counter to 0. Next signal is generated when counter is enabled
and has reached it’s maximum value 5 in case of mod 6 counter.
Digital Clock
The clock counts on each input clock event. Enable signal is input to allow the clock to count. Reset
signal allows to put clock in initial state of all 0. The HEX led display reflect the current time. The left

most two LEDs are hour values, middle two are minutes and right ones are seconds. The clock resets
to initial state on reaching a count 12:00:00.