Electrical Engineering: Data Representation and Digital Logic Homework

This assignment solution delves into the core concepts of data representation and digital logic. It begins with number system conversions, including converting between hexadecimal, base-8, and binary formats, and converting fractional numbers. The solution then explores complement representations, including one's complement, two's complement, and signed magnitude, analyzing the representation of positive and negative numbers. Furthermore, the assignment covers Boolean algebra, demonstrating the equivalence of logical expressions using truth tables and De Morgan's Law. The solution includes circuit simplification using logic gates, and the final part of the assignment provides a concise bibliography of relevant resources such as books on computer architecture and digital design.

Running head: DATA REPRESENTATION AND DIGITAL LOGIC
Data Representation and Digital Logic
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1DATA REPRESENTATION AND DIGITAL LOGIC
Question 1:
a) Given (152) x= (6A) 16
 X2 + (5 * X1) + (2 * X0) = (6 * 161) + (10 * 160)
 X2 + 5X + 2 = 106
 X2 + 5X - 104 = 0
 X2 + 13X - 8X – 104 = 0
 X(X + 13) – 8(X + 13) = 0
 (X - 8) (X + 13) = 0
 X = 8 and X = -13
Therefore, X is 8.
(152)8= (6A) 16
b) i) BED = (B * 162) + (E * 161) + (D * 160)
= 2816 + 224 + 13
= (3053)10
(3053)10 =
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2DATA REPRESENTATION AND DIGITAL LOGIC
BED16 = (11012002)3
ii) (321)7 = (3 * 72) + (2 * 71) + (1 * 70)
= (162)10
Again, (162)10 =
(162)10 = (10100010)2
iii) Conversion
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3DATA REPRESENTATION AND DIGITAL LOGIC
Therefore, (1235)10 = (2323)8
iv) For given 21.218 = (2 * 81) + (1 * 80). (2 * 8-1) + (1 * 7=8-2)
= 17 + 0.25 + 0.015625
= 17.265625
(21.21)8 = 17.265625
c) i) Negative number for one’s compliment = 100
Positive number for one’s compliment = 100
ii) Negative number for two’s compliment = 101
Positive number for two’s compliment = 011
iii) Negative number for signed magnitude = 111
Positive number for signed magnitude = 011
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4DATA REPRESENTATION AND DIGITAL LOGIC
Question 2:
a) After generating the output from L.H.S.
A B C D
0 0 0 1
0 1 0 1
1 0 0 1
1 1 1 0
After generating the output from R.H.S.
A B C D E
0 0 1 1 1
0 1 1 0 1
1 0 0 1 1
1 1 0 0 0
So, L.H.S. is equal to R.H.S.
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5DATA REPRESENTATION AND DIGITAL LOGIC
b) The two not gate and the and can be minimized as
Can be represented by
Therefore, finalized circuit is
c) X’ + Y’ + XYZ’
= X’ + Y’ + (X’ + Y’ + Z)’ [From De-Morgan’s Law]
= (XY (X’ + Y’ + Z))’ [From De-Morgan’s Law]
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6DATA REPRESENTATION AND DIGITAL LOGIC
= (XX’Y + XYY’ + XYZ)
= (0 + 0 + XYZ)
= (XYZ)’
= X’ + Y’ + Z’ [From De-Morgan’s Law]
= X’ + Y’ + XYZ’ = X’ + Y’ + Z’ [HENCE, PROVED]
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7DATA REPRESENTATION AND DIGITAL LOGIC
Bibliography
Harris, S., & Harris, D. (2015). Digital Design and Computer Architecture: ARM Edition.
Morgan Kaufmann.
Wang, S., & ZHANG, C. (2016). Computer architecture.
Impagliazzo, J., Pow-Sang, J. A., Trejos, I., Meier, R., & Nunes, D. J. (2017, March). Latin and
American perspectives on the computer engineering (CE2016) report. In World Engineering
Education Conference (EDUNINE), IEEE (pp. 9-13). IEEE.
Tanenbaum, A. S. (2016). Structured computer organization. Pearson Education India.
Comer, D. (2017). Essentials of computer architecture. CRC Press.
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