UHI Electrical and Electronics 1 (UH607003) Coursework 2 Solutions

This document presents a comprehensive solution to an Electrical and Electronics 1 coursework assignment. The solution addresses various aspects of electrical and electronic engineering, including the definition of fundamental terms like current, impedance, voltage, and power, and the application of Kirchhoff's voltage law in circuit analysis with a labelled diagram. The solution further explores AC sinusoidal voltage waveforms, bridge rectifiers, smoothing capacitors, and Zener diodes for DC voltage regulation. It also covers transistor operation in common emitter mode, including design procedures and the role of coupling and bypass capacitors. Additionally, the solution delves into binary number conversions, logic gate analysis, and the application of DeMorgan's theorem for logic expression simplification. The assignment covers a wide array of topics and provides detailed explanations and calculations to demonstrate a strong understanding of electrical and electronics principles.

Solutions
Sol-3
Part-(a) V pk = √ 2*V rms=1.414*110 =155.5 V
Period = T = 1/frequency = 1/60 = 0.017 sec = 17 ms
The waveform of AC sinusoidal voltage can be written as
v(t) = V pk∗¿sin(2π f t ¿ = 155.5∗¿sin(2π∗60∗t ¿
Part-(b) (i) In the following diagram, the input voltage waveform has peak voltage Vi =6 V and
frequency f = 60 Hz(assumption). Therefore, the output voltage waveform across the Bridge rectifier
has peak voltage Vo =(6 – 1.4)=4.6 V due to voltage drop of two diodes. And the output waveform
has frequency f ‘ =2*60 = 120 Hz.
(ii) Ripple voltage Vrp = V o
f '∗C∗RL
= 4.6
2∗60∗200 μ∗1.5 k =¿128 mV
(iii) In the below diagram, the zener diode has max power rating PZmax=1 W(assumption) and V Z =2
V(To regulate dc supply of 2 V). So, I Z max= PZmax / V Z = ½ =500 mA
Also, load current I L= 2/ RL= 2/1.5k =0.133 mA
 I s=I Zmax + IL=500+0.133 ≈ 500.13 mA
Therefore, Rsmin = ((V ¿¿ o−V Z)/ Is=(4.6−2)/500.13 m=5.2 Ω ¿

So, the bridge rectifier ckt with smoothing capacitor and Zener diode to regulate dc voltage can be
drawn as
Part-(c) When a transistor operates in common emitter mode, hFE is the DC current gain.
V CC =9 V , hFE =200 ,iC=5 m A
(i) iC=hFE∗iB
¿>iB= iC
hFE
= 5 m
200 =25 μ A
(ii) By design procedure, VE = 10% of VCC = 0.9 V
VC = VCC/2 =4.5 V
RC= V CC−V C
I C
= 4.5
5 m =900 Ω
RE= V E
I E
≈ 0.9
5 m =1.8 K Ω
R2=10*RE=18 KΩ
VB= R2
R1+ R2
∗V CC= 18 K
R1 +18 K ∗9=0.9+0.7=1.6
 18 K * 9 = 1.6*(R1 +18 K)
 R1 = 18*7.4 K/16 = 83.25 KΩ
Hence, the resistor values are:

RC ¿ 900 Ω, RE ¿ 1.8 KΩ, R1 = 83.25 KΩ, R2 = 18 KΩ
(iii) CC is called the coupling capacitor as it couples one stage of amplifier to the next stage
without affecting each stage’s DC biasing. This is achieved by the property of capacitor to
permit passage of only AC signals and block the DC component.
CE is also included in the parallel with the RE. This capacitor behaves as bypass capacitor
since it offers a low reactance path compared to RE resistance. So, the amplified AC signal
gets bypassed through the capacitance. This capacitor acts as open circuit for DC biasing
signals and short circuit for the high-frequency AC signals.
(iv)
Part-(d) Av=V o ut
V i n
=−Rf
Ri
 Rf
Ri
=−5.25
0.3 =17.5
 Rf =17.5∗Ri
Therefore, if Ri=10 KΩ , then Rf =175 KΩ

Sol-4
Part-(a)(i) keep dividing decimal number by 2 and store the remainders as shown below
Then, read the remainder sequence in reverse i.e upward direction as 11101001.
So, (233)10 = (11101001)2
(ii)Multiply each bit with its corresponding weight i.e power of 2 and add all. So,
(10110001)2 = 20+24+25+27 = 1+16+32+128 = (177)10
Part-(b) The logic equation for the given ckt can be written as
Z= A . B . C+ ( B .C + B .C ) =P+Q
where P = A . B . C and Q = ( B .C +B . C )

The Truth table for the above logic expression is given as
Part-(c) =𝑄 A . B . C . D+ A . B . C . D+ A . B . C . D+ A . B .C . D+ A . B .C . D
(i)By DeMorgan’s theorem, the value of Q expression will not change if any term like A . B . C . D
term gets added twice so,
𝑄 = A . B . C . D+ A . B . C . D+ A . B . C . D+ A . B .C . D+ A . B .C . D+ A . B . C . D
Taking out common terms,
𝑄 = A . C . D ( B+ B ) + A . C . D ( B+ B ) + A . B . D ( C+C )
As X + X=1 ,
𝑄 = A . C . D + A . C . D + A . B . D
Again, taking out common terms,
Q=C . D ( A+ A ) + A . B . D=C . D+ A . B . D
(ii)
Part-(d) Z=A + B+C
Z can be written as Z= A+ B+C
By DeMorgan’s second theorem,

X +Y =X . Y
Applying the theorem for B and C variables, we get
Z= A+B+C= A+ B .C
Now, again, applying the same theorem,
Z= A . B . C
Now, A can be implemented using NAND gate by giving same input A to all the input
pins of NAND gate. Similarly, for B.