MARIE Assembly Program for Fibonacci Sequence Calculation and ISA

This assignment presents a solution involving a MARIE assembly language program designed to calculate the Fibonacci sequence based on user input. The program takes an integer 'n' as input and computes the nth Fibonacci number. The solution includes the assembly code with detailed comments explaining each step, such as input handling, loop implementation, and output display. Additionally, the assignment addresses the limitations of the MARIE architecture concerning the maximum value of 'n' for accurate results due to integer limits. Furthermore, it explores Instruction Set Architecture (ISA) concepts by analyzing the number of possible instructions for a given address space and comparing code implementations across 3-address, 2-address, 1-address, and 0-address machines, illustrating the trade-offs in instruction complexity and memory usage. The document concludes with a bibliography of relevant computer architecture resources. Desklib provides access to this and many other solved assignments for students.

Running head: ASSESSMENT ITEM 4
Assignment 2: MARIE and ISA
Name of the Student
Name of the University
Author’s Note

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ASSESSMENT ITEM 4
Table of Contents
Answer to Question 1:.....................................................................................................................2
Answer to Question 2:.....................................................................................................................5
Answer to Question 3:.....................................................................................................................6
Bibliography....................................................................................................................................8

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ASSESSMENT ITEM 4
Answer to Question 1:
1.a. MARIE program for the calculation of Fib(n) where user inputs = n is given below:
ORG 100
Input Input number
Store N // Input from the user is taken for printing the number of terms
Store Ctr // It is used for storing the variable of the counter to the accumulator
Loop1, Clear
Load Ctr // The valu of the counter is loaded to the processor from the accumulator
Subt C1 // A substraction is done with the value of C1
Store Ctr
Load F2 // The value of F2 is loaded on the accumulator
Add F1 // An addition of F1 is done with the F2
Store F3 // The value of the addition is stored in F3 on the accumulator
Load F1 // The value of F1 is loaded on the accumulator
Store F2 // The value of F2 is stored on accumulator
Load F3
Store F1
Load Ctr

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ASSESSMENT ITEM 4
Skipcond 400 // A condition is applied for skipping the check condition
Jump Loop1 // JUmp is applied for jumping to the location 400
Load Ctr
Output
Load N // The Output value is N
Output
Load F1 // Final value of the output is displayed
Output
Halt // used for controlling the halts
N, DEC 0
Ctr, DEC 0
C1, DEC 1
F1, DEC 0
F2, DEC 1
F3, DEC 0

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ASSESSMENT ITEM 4
1.b. The maximum value of n for which the program can produce a correct result is 24 because
the limits of the integers are crossed by the system and storage has a limit to store the data type
and if the after analysis of the program code the following output is displayed for n =24. It shows
a negative value since the threshold has crossed or reached.

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ASSESSMENT ITEM 4
Answer to Question 2:
Number of possible instruction set for the 11 bits address = 211
= 2048
Number of encoding consumed by the two-address instructions = 6 × 24 × 24
= 1536
Number of encoding taken by the one-address instructions = 30 × 24
= 480
Therefore the possible number of zero-address instructions = 2048 − (1536 + 480)

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ASSESSMENT ITEM 4
= 32 instructions.
Answer to Question 3:
For the 3 Address Machine
ADD R1, B, C
SUBT R2, D, E
MUL A, R1, R2
For the 2 Address Machine
LOAD R1, B
ADD R1, C
LOAD R2, D
SUBT R2, E
MULT R2, R1
STORE A, R2
For the 1 Address machine
LOAD B
ADD C
STORE TEMP
LOAD D

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ASSESSMENT ITEM 4
SUBT E
MULT TEMP
STORE A
For the 0 address machine
PUSH B
PUSH C
ADD
PUSH D
PUSH E
SUB
MULT
STORE A

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ASSESSMENT ITEM 4
Bibliography
Levy, H., & Eckhouse, R. (2014). Computer programming and architecture: The VAX. Digital
Press.
Null, L., & Lobur, J. (2014). The essentials of computer organization and architecture. Jones &
Bartlett Publishers.
Omran, S. S., & Amory, I. A. (2017, November). Reconfigurable cache memory architecture
design based on VHDL. In Electrical and Computing Technologies and Applications
(ICECTA), 2017 International Conference on (pp. 1-6). IEEE.
Ritpurkar, S. P., Thakare, M. N., & Korde, G. D. (2015, January). Design and simulation of 32-
Bit RISC architecture based on MIPS using VHDL. In Advanced Computing and
Communication Systems, 2015 International Conference on(pp. 1-6). IEEE.
Tanenbaum, A. S. (2016). Structured computer organization. Pearson Education India.
Wang, S., & ZHANG, C. (2016). Computer architecture.
Wu, J., Li, L., & Wu. (2016). Advanced Computer Architecture. Springer Singapore.
Zagan, I., Gaitan, N. C., & Gaitan, V. G. (2017). An Approach of nMPRA Architecture using
Hardware Implemented Support for Event Prioritization and Treating. INTERNATIONAL
JOURNAL OF ADVANCED COMPUTER SCIENCE AND APPLICATIONS, 8(2), 40-45.