Research Methods: Managing Overheads in Partially Reconfigurable FPGAs

This report, focusing on research methods for engineers, investigates the management of overheads in partially reconfigurable Field Programmable Gate Arrays (FPGAs). It begins with an introduction to FPGAs and their increasing importance in various domains due to their programmability and reconfigurability. The literature review delves into the dynamic and static power consumption within reconfigurable computing systems, referencing key studies on power dissipation in logic, routing, and clocking resources. The review further examines the impact of leakage current, junction temperature, and chip resource utilization on static power consumption. Techniques for reducing leakage energy, such as region-limited placement and clock gating, are discussed. The report highlights the gaps in current research, particularly regarding the energy reduction potential of acceleration hardware, the use of partial reconfiguration in energy management, and the comparison of partial reconfiguration methods with alternatives like clock gating. The report concludes by referencing relevant research papers.

RESEARCH METHODS FOR ENGINEERS
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Title: MANAGING OVERHEADS IN PARTIALLY RECONFIGURABLE FPGAs
Introduction
Field programmable gate arrays, FPGAs, have developed from being chips that are used in the
implementation of glue-logic to arenas for implementation of advanced mixed systems of
hardware and software-on-chips. With their sizes and capabilities being on the increase, FPGAs
have established applications in an avalanche of domains in which their programmability
provides exclusive benefits compared to fixed applications [1]. An outstanding advantage of
reconfigurable computer systems revolves around their capability of reconfiguring hardware to
delivering high performance or reducing consumption of energy. Hence, reconfiguration
computing systems might attain the needs imposed by embedded systems. An integral part of
partial reconfiguration revolves around reconfiguration overhead that is often inclusive of
runtime reconfiguration time as well as the static storage space for reconfiguration data. The two
costs are directly linked with the physical partial reconfiguration file size. In as much as previous
researches have illustrated optimized accelerators, limited focus has been put on leverage of
runtime partial configuration property in reducing the consumption of energy by the chip.
Literature Review
Dynamic power and static power are the two major power consumption sources within a
reconfigurable computing system. Consumption of static power takes place due to leakage
current within transistor even as dynamic power consumption takes place when the transistor is
switching.
Shang et al. (2002) analyzed consumption of dynamic power of Xilinx Virtex-II FPGAs and
their findings demonstrated the role of dissipation of dynamic power for logic, routing as well as
clocking resources to be 16 per cent, 60 per cent and 14 per cent in that order [3]. Tuan et al.
(2003) explored leakage of power for a 90 nm FPGA with the aid of elaborate device-level
simulations and established that statistic consumption of static power was associated with inputs
to configuration memory, junction temperature as well as utilization of chip resource [5]. Li et al.
(2003) came up with power simulation for studying power efficiency in FPGAs within 0.10 um
technology where they established power leakage within deep sub-micron FPGAs may be to the
tune of 50% of cumulative power, emphasizing on the need of techniques for reducing static
power [4].

Tsai et al. (2004) suggested a reduction in the leakage energy within FPGAs with the aid of
region-limited placement [2]. The chip real estate within their arrangement is organized into
small locations and at runtime; unnecessary components may be turned off with the aid of sleep
transistors. Telikepalli (2006) in reporting a study made by Xilinx showed that there has been
exponential growth in static power with every new process being less than 2.5 microns with such
study reaffirming the statement static power is gaining responsible for the largest volumes of
cumulative consumption of power within FPGAs [1]. Still, they implanted techniques of clock
gating on Virtex-5 gadgets to in a selective manner turn on/off flip-flops which enable or disable
branches of distribution network of on-chop clock in a bid to lower the distribution power of the
clock. Paulsson et al. (2008) adopted dynamic clock scaling within Xilinx Spartan 3 systems
through carrying out runtime partial reconfiguration of Digital Clock Manager. Their findings
illustrated clock scaling resulted in power saving by 8% [6].
Wang et al. (2009) researched on the effect of clock power on overall power consumption of
chip and established a clock distribution power may contribute to the tune of 22 per cent of the
general consumption of power [7]. Liu et al. (2009) suggested the use of direct memory access
methods in direct transfer of configuration data to Internal Configuration Access Point in which
an 82 MB/s ICAP was reported throughout with the use of the approach [9]. In addition, they put
a block RAM cache close to ICAP to enhance the ICAP throughput to the tune of 378 MB/s.
nevertheless, as resources for on-chip storage tend to be limited in supply as well as scarce,
setting up a large BRAM close to the ICAP was not realistic. Partial reconfiguration was coupled
by Heiner et al. (2009) using configuration scrubbing [8]. They adopted a self-scrubber which
uses a small fraction of FPGA in reconfiguring a bigger fraction of design even as it continues to
scrub the whole FPGA. The reconfigurability of Virtex-5 FPGAs was conducted by Koch et al.
(2010) where they anticipated attaining a reconfiguration throughput of numerous GBs/s on
improved generations of FPGAs [10].

The Gaps
The following concerns are not addressed by the existing literature:
 Whether or not acceleration hardware result in reduction of energy due to execution time
reduction
 If partial reconfiguration may be used in reducing consumption of energy in
reconfigurable systems
 If partial recognition energy management methods are able to outshine other methods
including clock gating

References
[1] Telikepalli, A., 2006. Power vs. performance: The 90 nm inflection point reducing power
in FPGAs–The triple challenge. White Paper, 223, pp.1-18
[2] Gayasen, A., Tsai, Y., Vijaykrishnan, N., Kandemir, M., Irwin, M.J. and Tuan, T., 2004,
February. Reducing leakage energy in FPGAs using region-constrained placement.
In Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field
programmable gate arrays (pp. 51-58)
[3] Shang, L., Kaviani, A.S. and Bathala, K., 2002, February. Dynamic power consumption
in Virtex™-II FPGA family. In Proceedings of the 2002 ACM/SIGDA tenth international
symposium on Field-programmable gate arrays (pp. 157-164)
[4] Li, F., Chen, D., He, L. and Cong, J., 2003, February. Architecture evaluation for power-
efficient FPGAs. In Proceedings of the 2003 ACM/SIGDA eleventh international
symposium on Field programmable gate arrays (pp. 175-184)
[5] Tuan, T. and Lai, B., 2003, September. Leakage power analysis of a 90nm FPGA.
In Proceedings of the IEEE 2003 Custom Integrated Circuits Conference, 2003. (pp. 57-
60). IEEE
[6] Paulsson, K., Hübner, M. and Becker, J., 2006, August. On-line optimization of fpga
power-dissipation by exploiting run-time adaption of communication primitives.
In Proceedings of the 19th annual symposium on Integrated circuits and systems
design (pp. 173-178)
[7] Wang, Q., Gupta, S. and Anderson, J.H., 2009, February. Clock power reduction for
virtex-5 FPGAs. In Proceedings of the ACM/SIGDA international symposium on Field
programmable gate arrays (pp. 13-22)
[8] Heiner, J., Sellers, B., Wirthlin, M. and Kalb, J., 2009, August. FPGA partial
reconfiguration via configuration scrubbing. In 2009 International Conference on Field
Programmable Logic and Applications (pp. 99-104). IEEE
[9] Liu, S., Pittman, R.N. and Forin, A., 2010, February. Minimizing partial reconfiguration
overhead with fully streaming DMA engines and intelligent ICAP controller.
In FPGA (p. 292)
[10] Koch, D., Beckhoff, C. and Torrison, J., 2010, May. Fine-grained partial runtime
reconfiguration on Virtex-5 FPGAs. In 2010 18th IEEE Annual International Symposium
on Field-Programmable Custom Computing Machines (pp. 69-72). IEEE